5L35021 Datasheet

13

©2017-2025 Renesas Electronics Corporation

December 15, 2025

Table 19. DIFF2 Output

DFC – Dynamic Frequency Control

▪ OTP programmable–4 different feedback fractional dividers (4 VCO frequencies) that apply to PLL2.

▪ ORT (over shoot reduction) function will be applied automatically during the VCO frequency change.

▪ Smooth frequency incremental or decremental from current VCO to targeted VCO base on DFC hardware pins selection.

Figure 2. DFC Function Block Diagram

Table 20. DFC Function Priority

* The 5L35021 has only OE1 pin for DFC function hardware pin selection. For OE1/OE3 two pins DFC control, use 5L35023 24-QFN

package device.

DIFF2

B35<7>

B0<3>

From PLL1 + Divider 1

0

0

From PLL2 + Divider 3

1

0

From REF + Divider 1

0

1

DFC_EN bit (W32[4])

OE1_fun_sel

(W30[6:5])

*OE3_fun_sel

(W30[3:2])

SCL_DFC1

DFC[1:0]

Notes

0

x

x

x

0

DFC disable

1

11 (DFC)

00–10 (DFC)

x

[0,OE1]

One pin DFC–OE1

1

11 (DFC)

11 (DFC)

x

[OE3,OE1]

Two pin DFC–OE3,

OE1

1

00–10

11

x

Not permitted

Not supported

1

00–10

00–10

0

[SCL_DFC1,

SDA_DFC0]

I2C pin as DFC

control pins mode

1

00–10

00–10

1

W30[1:0]

I2C control DFC

mode

PLL2

M divider

N divider

N divider

N divider

N divider

Selector

00

01

10

11

DFC1:0

OTP/I2C

OUT DIV