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DRA752ABC Datasheet(PDF) 4 Page - Texas Instruments |
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DRA752ABC Datasheet(HTML) 4 Page - Texas Instruments |
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4 / 443 page  4 DRA756, DRA755, DRA754, DRA752 DRA751, DRA750, DRA746, DRA745, DRA744 SPRS950F – DECEMBER 2015 – REVISED MAY 2019 www.ti.com Submit Documentation Feedback Product Folder Links: DRA756 DRA755 DRA754 DRA752 DRA751 DRA750 DRA746 DRA745 DRA744 Table of Contents Copyright © 2015–2019, Texas Instruments Incorporated Table of Contents 1 Device Overview ......................................... 1 1.1 Features .............................................. 1 1.2 Applications ........................................... 2 1.3 Description ............................................ 2 1.4 Functional Block Diagram ........................... 3 2 Revision History ......................................... 5 3 Device Comparison ..................................... 6 3.1 Related Products ..................................... 9 4 Terminal Configuration and Functions ............ 10 4.1 Terminal Assignment ................................ 10 4.2 Ball Characteristics .................................. 11 4.3 Multiplexing Characteristics ......................... 80 4.4 Signal Descriptions .................................. 98 5 Specifications ......................................... 140 5.1 Absolute Maximum Ratings ........................ 140 5.2 ESD Ratings ....................................... 141 5.3 Power on Hour (POH) Limits ...................... 142 5.4 Recommended Operating Conditions ............. 143 5.5 Operating Performance Points ..................... 146 5.6 Power Consumption Summary .................... 168 5.7 Electrical Characteristics ........................... 168 5.8 Thermal Resistance Characteristics ............... 177 5.9 Power Supply Sequences ......................... 179 6 Clock Specifications ................................. 188 6.1 Input Clock Specifications ......................... 189 6.2 RC On-die Oscillator Clock ........................ 197 6.3 DPLLs, DLLs Specifications ....................... 197 7 Timing Requirements and Switching Characteristics ........................................ 202 7.1 Timing Test Conditions ............................ 202 7.2 Interface Clock Specifications ..................... 202 7.3 Timing Parameters and Information ............... 202 7.4 Recommended Clock and Control Signal Transition Behavior ............................................ 204 7.5 Virtual and Manual I/O Timing Modes ............. 204 7.6 Video Input Ports (VIP) ............................ 207 7.7 Display Subsystem – Video Output Ports ......... 225 7.8 Display Subsystem – High-Definition Multimedia Interface (HDMI) ................................... 237 7.9 External Memory Interface (EMIF) ................. 237 7.10 General-Purpose Memory Controller (GPMC) ..... 237 7.11 Timers .............................................. 259 7.12 Inter-Integrated Circuit Interface (I2C) ............. 260 7.13 HDQ / 1-Wire Interface (HDQ1W) ................. 263 7.14 Universal Asynchronous Receiver Transmitter (UART) ............................................. 265 7.15 Multichannel Serial Peripheral Interface (McSPI) . 266 7.16 Quad Serial Peripheral Interface (QSPI) .......... 272 7.17 Multichannel Audio Serial Port (McASP) .......... 277 7.18 Universal Serial Bus (USB) ........................ 296 7.19 Serial Advanced Technology Attachment (SATA) . 298 7.20 Peripheral Component Interconnect Express (PCIe) .............................................. 298 7.21 Controller Area Network Interface (DCAN) ........ 299 7.22 Ethernet Interface (GMAC_SW) ................... 299 7.23 Media Local Bus (MLB) interface .................. 310 7.24 eMMC/SD/SDIO ................................... 313 7.25 General-Purpose Interface (GPIO) ................ 339 7.26 Audio Tracking Logic (ATL) ........................ 340 7.27 System and Miscellaneous interfaces ............. 340 7.28 Test Interfaces ..................................... 340 8 Applications, Implementation, and Layout ...... 345 8.1 Introduction ........................................ 345 8.2 Power Optimizations ............................... 346 8.3 Core Power Domains .............................. 360 8.4 Single-Ended Interfaces ........................... 372 8.5 Differential Interfaces .............................. 374 8.6 Clock Routing Guidelines .......................... 395 8.7 DDR2/DDR3 Board Design and Layout Guidelines .......................................... 397 9 Device and Documentation Support .............. 432 9.1 Device Nomenclature .............................. 432 9.2 Tools and Software ................................ 434 9.3 Documentation Support ............................ 435 9.4 Related Links ...................................... 435 9.5 Community Resources ............................. 436 9.6 Trademarks ........................................ 436 9.7 Electrostatic Discharge Caution ................... 436 9.8 Glossary ............................................ 436 10 Mechanical, Packaging, and Orderable Information ............................................. 437 10.1 Packaging Information ............................. 437 |
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