DRA752ABC datasheet(80/443 Pages) TI2

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Terminal Configuration and Functions

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Product Folder Links: DRA756 DRA755 DRA754 DRA752 DRA751 DRA750 DRA746 DRA745 DRA744

DRA756, DRA755, DRA754, DRA752

DRA751, DRA750, DRA746, DRA745, DRA744

SPRS950F – DECEMBER 2015 – REVISED MAY 2019

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(10) The internal pull resistors for balls K7, M7, J5, K6, J4, J6, H4, H5 are permanently disabled when sysboot15 is set to 1 as described in the section Sysboot Configuration of the Device

TRM. If internal pull-up/down resistors are desired on these balls then sysboot15 should be set to 0. If gpmc boot mode is used with SYSBOOT15=1 (not recommended) then external

pull-downs should be implemented to keep the address bus at logic-0 value during boot since the gpmc ms-address bits are high-z during boot.

4.3

Multiplexing Characteristics

Table 4-3 describes the device multiplexing (no characteristics are available in this table).

NOTE

This table doesn't take into account subsystem multiplexing signals. Subsystem multiplexing signals are described in Section 4.4, Signal

Descriptions.

NOTE

For more information, see the Control Module / Control Module Functional Description / PAD Functional Multiplexing and Configuration

section of the Device TRM.

NOTE

Configuring two pins to the same input signal is not supported as it can yield unexpected results. This can be easily prevented with the

proper software configuration. (Hi-Z mode is not an input signal.)

NOTE

When a pad is set into a multiplexing mode which is not defined by pin multiplexing, that pad’s behavior is undefined. This should be

avoided.

CAUTION

The I/O timings provided in Section 7, Timing Requirements and Switching Characteristics are valid only if signals within

a single IOSET are used. The IOSETs are defined in the corresponding tables.

Table 4-3. Multiplexing Characteristics

ADDRESS

BALL

NUMBER

MUXMODE FIELD SETTINGS (CTRL_CORE_PAD_*[3:0])

P25

ddr2_a6

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