ETA3006

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ETA3006 Rev 1.0

PIN DESCRIPTION

PIN#

NAME

DESCRIPTION

1

BATN

Negative terminal sense voltage input and common

Ground pin.

2

BST

Bootstrap pin. Connect a 100nF capacitor from BST to SW.

3

ISET

Balancing current setting pin. Connect a resistor from SW to an inductor to

program

the

balancing

current.

Under

an

extremely

high

noise

environment, a 1nF capacitor between ISET pin and SW pin can improve

the ISET voltage stability, so a capacitor position reservation here is

recommended.

4

BATPS

Sense voltage input for top cell. Connect a 10µF capacitor between BATPS

and BATN.

5

BATC

Sense voltage input for bottom cell. Connect a 22µF capacitor between

BATC and BATN.

6

BATP

Power input from top cell. Connect a 22µF capacitor between BATP and

BATC.

7

TEST

Factory Use Only. Float this Pin.

8

SW

Switching node. Connected to an inductor.

FUNCTIONAL BLOCK DIAGRAM

ETA3006

Bandgap

& VDD

& BIAS

& OVP

& TSD

1uA

UVLO

Timer

Control

Balance

Current

Sense

Battery

Sense

VDD

ISET

BATPS

Balance

Control

BATC

BST

SW

BATN

BATP

Figure 2: Functional Block Diagram