ETA3006

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8

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ETA3006 Rev 1.0

Figure 3:

State Machine Diagram

The ETA3006 timing diagram for state machine is shown in following figure.

Figure 4: Timing Profile

UNBALANCE DETECTION

When state is in CHECK State, ETA3006 detects VKICK difference between 2 cells to enter BALANCE State.

If the top cell voltage is higher, balancing will be “DOWN”, meaning discharge the top cell to charge to

bottom cell. And if the bottom cell voltage is higher, balancing will be “UP”, meaning discharge the bottom

cell to charge to top cell.

BALANCING PROFILE

ETA3006 balancing always starts with “Constant Current

Regulation” phase since it is always with high voltage

difference. Constant current is set by RISET.

When the detected difference at IC pin is almost zero, but due

to battery equivalent series resistance, real difference is not

zero, then current is not immediately zero but reduced slowly

depend on battery capacitance. This condition is called

“Current Dimming” phase.

When two cell voltages are equal, balancing current becomes

almost zero, when this persists for a time period of TDONE, the

balancing finishes one cycle, and ETA3006 goes back to

Figure 5:

Balancing Profile

SLEEP

STATE

CHECK

STATE

BALANCE

STATE

TSLEEP

Expired

TCHECK

Expired

TALLOW Expired and

Unbalance Detected

TSD or OVP

Skipping and

TDONE Expired

VBATP < UVLO

Any State

nUVLO and

EN

2s TIMER

TCHECK

BALANCING

DONE

TSLEEP

TSLEEP

Constant

Current

Current

Dimming

Skip

TDONE

Delta Voltage

(At IC pin Measurement)

TDONE

Constant Current

Current Dimming

Inductor Current