Silan

Microelectronics

SD6834_Datasheet

FUNCTION DESCRIPTION

SD6834 is designed for off-line SMPS, consisting of high voltage MOSFET, optimized gate driver and current mode

PWM+PFM controller which includes frequency oscillator and various protections such as undervoltage lockout,

overvoltage protection, overload protection, primary winding overcurrent protection and over temperature protection.

Frequency jitter generated from oscillator is used to lower EMI. Burst mode is adopted during light load to lower

standby power dissipation, and function of lead edge blanking eliminates the MOSFET error shutdown caused by

interference through minimizing MOSFET turning on time. Peak current compensation reduces the pressure on

transformer during circuit starts and output power limit can be adjusted by resistor through CS pin. Few peripheral

components are needed for higher efficiency and higher reliability and it is suitable for flyback converter and forward

converter.

1.

Under Voltage Lockout and Self-Start

At the beginning, the capacitor connected to pin VCC is charged via start resistor by high voltage AC and the circuit

starts to work if voltage at VCC is 15.5V. The output and FB source current are shutdown if there is any protection

during normal operation and VCC is decreased because of powering of auxiliary winding. The whole control circuit is

shutdown if voltage at VCC is 8.3V below to lower current dissipation and the capacitor is recharged for restarting.

0

VCC

VSTART

VSTOP

0

ICC

t

t

Powered by

start resistor

Powered by

assistant winding

Powered by start resistor

2.

Frequency Jitter and reduced frequency mode

The oscillation frequency is kept changed for low EMI and decreasing radiation on one frequency. The oscillation

frequency changes within a very small range to simplify EMI design. The rule of frequency changing (frequency center

is 67KHz): ±2.5KHz change in 4ms, 63 frequency points in all.

For high efficiency, reduced frequency mode is adopted with two methods:

1.

Frequency is reduced according to current output from FB pin. If IFB is higher than I1, the frequency f decreases

from 67KHz and f is 25KHz when the IFB increases to I2 or higher. This is shown in left diagram below.

2.

IPK is changed according to IFB, shown in right diagram below.

HANGZHOU SILAN MICROELECTRONICS CO.,LTD

Rev.:1.5

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