TMS320VC5502 datasheet(33/190 Pages) TI

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3.1.2

On-Chip Dual-Access RAM (DARAM)

3.1.3

Instruction Cache

TMS320VC5502

Fixed-Point Digital Signal Processor

SPRS166J – APRIL 2001 – REVISED AUGUST 2006

TMS320VC5502 features 32K x 16-bit (64K bytes) of on-chip dual-access RAM. This memory enhances

system performance, since the C55x CPU can access a DARAM block twice per machine cycle. The

DARAM is composed of 8 blocks of 4K x 16-bit each (see Table 3-2). Each block in the DARAM can

support two reads in one cycle, a read and a write in one cycle, or two writes in one cycle. The

dual-access RAM is located in the (byte) address range 000000h-00FFFFh, it can be accessed by the

program, data and DMA buses. The HPI has NO access to the DARAM block when device is in reset.

Table 3-2. DARAM Blocks

BYTE ADDRESS RANGE

MEMORY BLOCK

000000h – 001FFFh

DARAM 0(1)

002000h – 003FFFh

DARAM 1

004000h – 005FFFh

DARAM 2

006000h – 007FFFh

DARAM 3

008000h – 009FFFh

DARAM 4

00A000h – 00BFFFh

DARAM 5

00C000h – 00DFFFh

DARAM 6

00E000h – 00FFFFh

DARAM 7

(1)

First 192 bytes are reserved for Memory-Mapped Registers (MMRs).

On the TMS320VC5502, instructions may reside in internal memory or external memory. When

instructions reside in external memory, the I-Cache can improve the overall system performance by

buffering the most recent instructions accessed by the CPU.

The 5502 includes a 16K-byte instruction cache, which consists of a single 2-way cache block. The 2-way

cache uses 2-way associative mapping and holds up to 16K bytes: 512 sets, two lines per set, four 32-bit

words per line. In the 2-way cache, each line is identified by a unique tag. The 2-way cache is updated

based on a least-recently-used algorithm.

Control bits in the CPU status register ST3_55 provide the ability to enable, freeze, and flush the cache.

For more information on the instruction cache, see the TMS320VC5501/5502 DSP Instruction Cache

Reference Guide (literature number SPRU630).

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