TMS320VC5502 datasheet(81/190 Pages) TI

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TMS320VC5502

Fixed-Point Digital Signal Processor

SPRS166J – APRIL 2001 – REVISED AUGUST 2006

Table 3-30. Peripheral IDLE Control Register Bit Field Description (continued)

BIT NAME

BIT NO.

ACCESS

RESET VALUE

DESCRIPTION

6(1)

R/W

ID bit

•

ID = 0:

ID remains active when ISTR.PERIS = 1 and the IDLE

instruction is executed.

•

ID = 1:

ID is disabled when ISTR.PERIS = 1 and the IDLE instruction is

executed.

5(1)

R/W

IO bit

•

IO = 0:

GPIO remains active when ISTR.PERIS = 1 and the IDLE

instruction is executed.

•

IO = 1:

GPIO is disabled when ISTR.PERIS = 1 and the IDLE instruction

is executed.

SP2

4(1)

R/W

McBSP2 bit

•

SP2 = 0:

McBSP2 remains active when ISTR.PERIS = 1 and the IDLE

instruction is executed.

•

SP2 = 1:

McBSP2 is disabled when ISTR.PERIS = 1 and the IDLE

instruction is executed.

SP1

3(1)

R/W

McBSP1 bit

•

SP1 = 0:

McBSP1 remains active when ISTR.PERIS = 1 and the IDLE

instruction is executed.

•

SP1 = 1:

McBSP1 is disabled when ISTR.PERIS = 1 and the IDLE

instruction is executed.

SP0

2(1)

R/W

McBSP0 bit

•

SP0 = 0:

McBSP0 remains active when ISTR.PERIS = 1 and the IDLE

instruction is executed.

•

SP0 = 1:

McBSP0 is disabled when ISTR.PERIS = 1 and the IDLE

instruction is executed.

TIM1

1(1)

R/W

TIMER1 bit

•

TIM1 = 0:

TIMER1 remains active when ISTR.PERIS = 1 and the IDLE

instruction is executed.

•

TIM1 = 1:

TIMER1 is disabled when ISTR.PERIS = 1 and the IDLE

instruction is executed.

TIM0

0(1)

R/W

TIMER0 bit

•

TIM0 = 0:

TIMER0 remains active when ISTR.PERIS = 1 and the IDLE

instruction is executed.

•

TIM0 = 1:

TIMER0 is disabled when ISTR.PERIS = 1 and the IDLE

instruction is executed.

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