TMS320VC5502 datasheet(49/190 Pages) TI

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3.8

Host-Port Interface (HPI)

TMS320VC5502

Fixed-Point Digital Signal Processor

SPRS166J – APRIL 2001 – REVISED AUGUST 2006

The 5502 HPI provides an interface to a host with the following features:

• 16-bit host address bus and 16-bit host data bus (non-multiplexed mode only)

• Multiplexed and non-multiplexed modes

• Host access to on-chip DARAM (excluding CPU memory-mapped registers)

• 16-bit address register with autoincrement capability for faster transfers

• Multiple address/data strobes provide a glueless interface to a variety of hosts

• HRDY signal for handshaking with host

The 5502 HPI can access the entire DARAM space of the 5502 (excluding memory-mapped CPU

registers); however, it does not have access to external memory of the peripheral I/O space. Furthermore,

the HPI cannot access internal DARAM space when the device is in reset. Note that all accesses made

through the HPI are word-addressed.

NOTE

No host access should occur when the HPI is placed in IDLE. The host cannot wake up

the DSP through the DSP_INT bit of the HPIC register when the DSP is in IDLE mode.

The 5502 HPI supports both multiplexed 8-bit and non-multiplexed 16-bit modes. One of these two modes

can be selected via the GPIO6 pin. At reset, if GPIO6 is low, the HPI non-multiplexed 16-bit mode is

enabled and some of the HPI signals can be used as GPIOs. If GPIO6 is high, the HPI can be used in

multiplexed 8-bit mode. Similarly, some of the HPI signals can be used as GPIOs. (See Section 3.3.2,

Host Port Mux, for more information on pin multiplexing for both modes of the HPI.)

When GPIO6 is low at reset, the 5502 HPI will be configured in non-multiplexed mode. In this mode, pins

A[17:2] and pins D[15:0] of the Parallel Port Mux will be set to HPI.HA[15:0] and HPI.HD[15:0],

respectively. In non-multiplexed mode, the host can read/write 16-bit data from the 5502's internal memory

by using the 16-bit address and data bus and the HPI control signals [see the TMS320VC5501/5502 DSP

Host Port Interface (HPI) Reference Guide (literature number SPRU620) for more information on the 5502

HPI]. Note that in this mode, the 5502 EMIF wil be disabled.

When GPIO6 is high at reset, the 5502 HPI will be configured in multiplexed mode. In this mode, pins

HD[7:0], HC0, and HC1 of the Host Port Mux will be set to HPI.HD[7:0], HPI.HAS, and HPI.HBIL,

respectively. In multiplexed mode, the host can only send 8 bits of data at a time through the HPI.HD[7:0]

bus; therefore, some extra steps have to be taken to read/write from the 5502's internal memory [see the

TMS320VC5501/5502 DSP Host Port Interface (HPI) Reference Guide (literature number SPRU620) for

more information on the 5502 HPI]. Note that in this mode, the EMIF is fully enabled.

The 5502 HPI has its own register set, therefore the HINT bit of CPU register ST3_55 is not used for

DSP-to-host interrrupts. The HINT bit in the Host Port Control Register (HPIC) should be used for

DSP-to-host interrupts.

A host must not initiate any transfer requests from the HPI while the HPI is being brought out of reset. As

described in Section 3.10.6, Reset Sequence, the C55x CPU and the peripherals are not brought out of

reset immediately after the RESET pin transitions from low to high. Instead, an internal counter stretches

the reset signal to allow enough time for the internal oscillator to stabilize and also to allow the reset signal

to propagate through different parts of the device. The IACK pin will go low for two CPU clock cycles to

indicate that this internal reset signal has been deasserted. A host must follow one of these two

requirements before initiating transfer requests from the HPI:

1. Keep the HPIENA pin low until the internal reset signal has been deasserted.

2. Keep the HCS, HDS1, and HDS2 pins inactive until the internal reset signal has been deasserted.

Note that when the HPI bootmode is used, the GPIO4 pin can also be used to determine when the internal

reset signal has been deasserted as this pin is used by the HPI to signal to the host that it is ready to

receive access requests.

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