TMS320DM647 datasheet(41/182 Pages) TI

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3.2.3

Boot Complete (BOOTCMPLT) register

3.2.4

Priority Allocation (PRI_ALLOC)

TMS320DM647/TMS320DM648

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SPRS372B – MAY 2007 – REVISED APRIL 2008

The BOOTCMPLT register contains a BC (boot complete) field in bit 0, and a ERR (boot error) field in bits

19:16.

The BC field is written by the external host to indicates that it has completed boot. In the bootloader code,

the CPU can poll for this bit. Once this bit = 1, the CPU can begin executing from DSPBOOTADDR.

The ERR field is written by the bootloader software if the software detects a boot error. Coming out of a

boot, application software can read this field to determine if boot was accomplished. Actual error code is

determined by software.

Figure 3-3. BOOTCMPLT Register 3

Reserved

ERR

R-0

Reserved

R-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 3-5. BOOTCMPLT Register Field Descriptions

Bit

Field

Value

Description

31:20

Reserved

19:16

ERR

Boot error

0000

No error

0001 – 1111

Bootloader software detected boot error. For details on boot errors, see the Using the

TMS320DM647x Bootloader Application Note (literature number SPRAAJ1).

15:1

Reserved

Boot Complete Flag from host. This is applicable only to host boots.

Host has not completed booting this device.

Host has completed booting this device and the DSP can begin executing from

DSPBOOTADDR.

Each of the masters (excluding the C64x+ Megamodule) is assigned a priority via the Priority Allocation

vying for the same endpoint. A value of 000b has the highest priority, while 111b has the lowest priority.

Note that the configuration SCR port on the data SCR is considered a single endpoint meaning priority will

be enforced when multiple masters try to access the configuration SCR. Priority is also enforced on the

configuration SCR side when a master (through the data SCR) tries to access the same endpoint as the

C64x+ Megamodule.

The Ethernet Subsystem and VLYNQ fields specify the priority of the Ethernet Subsystem and VLYNQ

peripherals, respectively. Similarly, the HOST field applies to the priority of the HPI and PCI peripherals.

Other master peripherals are not present in the PRI_ALLOC register as they have their own registers to

program their priorities. For more information on the default priority values in these peripheral registers,

see the device-compatible peripheral reference guides.

TI recommends that these priority registers be reprogrammed during device initialization.

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