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TMS320DM647 Datasheet(PDF) 99 Page - Texas Instruments |
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TMS320DM647 Datasheet(HTML) 99 Page - Texas Instruments |
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99 / 182 page  6.9.3.4 Placement A1 A1 X Y OFFSET RecommendedDDR2Device Orientation Y Y OFFSET DDR2 Device DM648 TMS320DM647/TMS320DM648 Digital Media Processor www.ti.com SPRS372B – MAY 2007 – REVISED APRIL 2008 Table 6-30. PCB Stack Up Specifications NO. PARAMETER MIN TYP MAX UNIT 1 PCB Routing/Plane Layers 6 2 Signal Routing Layers 3 3 Full ground layers under DDR2 routing Region 2 4 Number of ground plane cuts allowed within DDR routing region 0 5 Number of ground reference planes required for each DDR2 routing layer 1 6 Number of layers between DDR2 routing layer and reference ground plane 0 7 PCB Routing Feature Size 4 Mils 8 PCB Trace Width w 4 Mils 8 PCB BGA escape via pad size 18 Mils 9 PCB BGA escape via hole size 8 Mils 10 DSP Device BGA pad size(1) 11 DDR2 Device BGA pad size(2) 12 Single Ended Impedance, Zo 50 75 Ω 13 Impedance Control(3) Z-5 Z Z+5 Ω (1) See the Flip Chip Ball Grid Array Package Reference Guide (SPRU811) for DSP device BGA pad size. (2) See the DDR2 device manufacturer documenation for the DDR2 device BGA pad size. (3) Z is the nominal singled ended impedance selected for the PCB specified by item 12. Figure 6-14 shows the required placement for the DM647 device as well as the DDR2 devices. The dimensions for Figure 6-14 are defined in Table 6-31. The placement does not restrict the side of the PCB where the devices are mounted. The purpose of the placement is to limit the maximum trace lengths and allow for proper routing space. For 16-bit DDR memory systems, the high word DDR2 device is omitted from the placement. Figure 6-14. DM647/DM648 and DDR2 Device Placement Submit Documentation Feedback Peripheral Information and Electrical Specifications 99 |
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