TMS320DM647 datasheet(102/182 Pages) TI

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6.9.3.7 High-Speed Bypass Capacitors

6.9.3.8 Net Classes

TMS320DM647/TMS320DM648

Digital Media Processor

SPRS372B – MAY 2007 – REVISED APRIL 2008

www.ti.com

High-Speed (HS) bypass capacitors are critical for proper DDR2 interface operation. It is particularly

important to minimize the parasitic series inductance of the HS bypass cap, DSP/DDR power, and

DSP/DDR ground connections. Table 6-33 contains the specification for the HS bypass capacitors as well

as for the power connections on the PCB.

Table 6-34 lists the clock net classes for the DDR2 interface. Table 6-35 lists the signal net classes, and

associated clock net classes, for the signals in the DDR2 interface. These net classes are used for the

termination and routing rules that follow.

Table 6-33. High-Speed Bypass Capacitors

NO.

PARAMETER

MIN

MAX

UNIT

HS Bypass Capacitor Package Size(1)

0402

10 Mils

Distance from HS bypass capacitor to device being bypassed

250

Mils

Number of connection vias for each HS bypass capacitor(2)

Vias

Trace length from bypass capacitor contact to connection via

Mils

Number of connection vias for each DDR2 device power or ground balls

Vias

Trace length from DDR2 device power ball to connection via

Mils

DVDD18 HS Bypass Capacitor Count

(3)

Devices

DVDD18 HS Bypass Capacitor Total Capacitance

1.2

µF

DDR#1 HS Bypass Capacitor Count(3)

Devices

DDR#1 HS Bypass Capacitor Total Capacitance

0.4

µF

DDR#2 HS Bypass Capacitor Count(3)(4)

Devices

DDR#2 HS Bypass Capacitor Total Capacitance(4)

0.4

µF

(1)

× W, 10 mil units ( i.e., a 0402 is a 40 × 20 mil surface mount capacitor)

(2)

An additional HS bypass capacitor can share the connection vias only if it is mounted on the opposite side of the board.

(3)

These devices should be placed as close as possible to the device being bypassed.

(4)

Only used on 32-bit wide DDR2 memory systems

102

Peripheral Information and Electrical Specifications

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