TMS320DM647 datasheet(106/182 Pages) TI

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DM648

TMS320DM647/TMS320DM648

Digital Media Processor

SPRS372B – MAY 2007 – REVISED APRIL 2008

www.ti.com

Table 6-38. DQS and DQ Routing Specification (1)

NO.

PARAMETER

MIN

TYP

MAX

UNIT

Center to center DQS-DQS spacing

2 w

DQS E Skew Length Mismatch

Mils

Center to center DQS to other DDR2 trace spacing(2)

4 w

DQS/DQ nominal trace length(1)(3)(4)(5)

DQLM-50

DQLM

DQLM+50

Mils

DQ to DQS Skew Length Mismatch(3)(4)(5)

100

Mils

DQ to DQ Skew Length Mismatch(3)(4)(5)

100

Mils

Center to center DQ to other DDR2 trace spacing(2)(6)

4 w

Center to Center DQ to other DQ trace spacing(7)(2)

DQ/DQS E Skew Length Mismatch(3)(4)(5)

100

Mils

(1)

Series terminator, if used, should be located closest to DDR.

(2)

Center to center spacing is allowed to fall to minimum (w) for up to 500 mils of routed length to accommodate BGA escape and routing

congestion.

(3)

A 16-bit DDR memory system has two sets of data net classes, one for data byte 0, and one for data byte 1, each with an associated

DQS (2 DQSs).

(4)

A 32-bit DDR memory system will have four sets of data net classes, one each for data bytes 0 through 3, and each associated with a

DQS (4 DQSs).

(5)

There is no need and it is not recommended to skew match across data bytes, i.e., from DQS0 and data byte 0 to DQS1 and data byte

(6)

DQs from other DQS domains are considered other DDR2 trace.

(7)

DQLM is the longest Manhattan distance of each of the DQS and DQ net classes.

Figure 6-19 shows the routing for the DQGATE net classes. Table 6-39 contains the routing specification.

Figure 6-19. DQGATE Routing

Peripheral Information and Electrical Specifications

106

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