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TMS320DM647 Datasheet(PDF) 28 Page - Texas Instruments |
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TMS320DM647 Datasheet(HTML) 28 Page - Texas Instruments |
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28 / 182 page  TMS320DM647/TMS320DM648 Digital Media Processor SPRS372B – MAY 2007 – REVISED APRIL 2008 www.ti.com Table 2-4. TERMINAL FUNCTIONS (continued) TERMINAL NAME NO TYPE INTERNAL OPER DESCRIPTION PULLUP/ VOLT PULLDOWN VP4D02/ABE00 L2 I/O/Z IPU 3.3 V Video Port 4 Data 2 or EMIFA byte-enable control 0. Decoded from the low-order address bits. The number of address bits or byte enables used depends on the width of external memory. Byte-write enables for most types of memory. VP4D03/ABE01 M4 I/O/Z IPU 3.3 V Video Port 4 Data 3 or EMIFA byte-enable control 1. Number of address bits or byte enables used depends on the width of external memory. Byte-write enables for most types of memory. VP4D04/AEA10 M5 I/O/Z IPU 3.3 V Video Port 4 Data 4 or EMIFA External Address 10 (word address) (O/Z) VP4D05 M6 I/O/Z IPU 3.3 V Video Port 4 Data 5 VP4D06/ACE2 L3 I/O/Z IPU 3.3 V Video Port 4 Data 6 or EMIFA memory space enable 2 VP4D07/ACE3 L4 I/O/Z IPU 3.3 V Video Port 4 Data 7 or EMIFA memory space enable 3 VP4D08/AEA00 L5 I/O/Z IPD 3.3 V Video Port 4 Data 8 or EMIFA External Address 0 (word address) (O/Z) VP4D09/AEA01 K3 I/O/Z IPD 3.3 V Video Port 4 Data 9 or EMIFA External Address 1 (word address) (O/Z) VP4D12/AEA02 K4 I/O/Z IPD 3.3 V Video Port 4 Data 12 or EMIFA External Address 2 (word address) (O/Z) VP4D13/AEA03 L6 I/O/Z IPD 3.3 V Video Port 4 Data 13 or EMIFA External Address 3 (word address) (O/Z) VP4D14/AEA04 K5 I/O/Z IPD 3.3 V Video Port 4 Data 14 or EMIFA External Address 4 (word address) (O/Z) VP4D15/AEA05 J3 I/O/Z IPD 3.3 V Video Port 4 Data 15 or EMIFA External Address 5 (word address) (O/Z) VP4D16/AEA06 J4 I/O/Z IPD 3.3 V Video Port 4 Data 16 or EMIFA External Address 6 (word address) (O/Z) VP4D17/AEA07 J5 I/O/Z IPD 3.3 V Video Port 4 Data 17 or EMIFA External Address 7 (word address) (O/Z) VP4D18/AEA08 J6 I/O/Z IPD 3.3 V Video Port 4 Data 18 or EMIFA External Address 8 (word address) (O/Z) VP4D19/AEA09 K6 I/O/Z IPD 3.3 V Video Port 4 Data 19 or EMIFA External Address 9 (word address) (O/Z) EMIFA AEA23 H4 OZ IPD 3.3 V EMIFA External Address 23 (word address) (O/Z) AEA19 H5 O/Z IPU 3.3 V EMIFA External Address 19 (word address) (O/Z) AECLKINSEL/AEA17 G4 I/O/Z IPD 3.3 V Select EMIFA external clock (I) (The EMIFA input clock AECLKIN or SYSCLK4 is selected at reset via the pullup/pulldown resistor on this pin. Note: AECLKIN is the default for the EMIFA input clock.) or EMIFA external address 17 (word address) (O/Z) Table 2-5. TERMINAL FUNCTIONS (GROUND and POWER SUPPLY) TERMINAL NO TYPE INTERNAL OPER DESCRIPTION NAME PULLUP/PULL VOLT DOWN VSS A1 Ground VSS A5 Ground VSS A15 Ground VSS A18 Ground VSS A23 Ground VSS C4 Ground VSS D9 Ground Device Overview 28 Submit Documentation Feedback |
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