TMS320DM647 datasheet(69/182 Pages) TI

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6.6 Enhanced Direct Memory Access (EDMA3) Controller

6.6.1

EDMA3 Channel Synchronization Events

TMS320DM647/TMS320DM648

Digital Media Processor

www.ti.com

SPRS372B – MAY 2007 – REVISED APRIL 2008

Table 6-12. PLL2 and Reset Controller Registers Memory Map

HEX ADDRESS RANGE

DESCRIPTION

0x0212 0000

PID

Peripheral Identification and Revision Information Register

0x0212 0100

PLLCTL

PLL Controller 2 Operations Control Register

0x0212 0110

PLLM

PLL Controller 2 Multiplier Control Register

0x0212 0138

PLLCMD

PLL Controller 2 Command Register

0x0212 013C

PLLSTAT

PLL Controller 2 Status Register (Shows PLLC1 Status)

The EDMA controller handles all data transfers between memories and the device slave peripherals on

the

device.

These

data

transfers

include

cache

servicing,

non-cacheable

memory

accesses,

user-programmed data transfers, and host accesses. These are summarized as follows:

• Transfer to/from on-chip memories

–

DSP L1D memory

–

DSP L2 memory

• Transfer to/from external storage

–

DDR2 SDRAM

–

Synchronous/Asynchronous EMIF (EMIFA)

• Transfer to/from peripherals/hosts

–

VLYNQ

–

HPI

–

McASP

–

UART

–

Video Port 0/1/2/3/4

–

Timer 0/1/2/3

–

SPI

–

I2C

The EDMA supports up to 64 EDMA channels that service peripheral devices and external memory.

Table 6-13 lists the source of EDMA synchronization events associated with each of the programmable

EDMA channels. For the DM648 device, the association of an event to a channel is fixed; each of the

EDMA channels has one specific event associated with it. These specific events are captured in the

EDMA event registers (ER, ERH) even if the events are disabled by the EDMA event enable registers

(EER, EERH). For more detailed information on the EDMA module and how EDMA events are enabled,

captured, processed, linked, chained, and cleared, etc., see the TMS320DM647/DM648 DSP Enhanced

DMA (EDMA) Controller User's Guide (literature number SPRUEL2).

Table 6-13. EDMA Channel Synchronization Events

TPCC

DEFAUL BINARY

DEFAULT EVENT

TPCC

DEFAULT BINARY

DEFAULT EVENT

CHANN

CHANNEL

EVENT #

EVENT#

000 0000

HPI/PCI : DSPINT

010 0000

VP2EVTYA

000 0001

TIMER0 : TINT0L

010 0001

VP2EVTCbA

000 0010

TIMER0 : TINT0H

010 0010

VP2EVTCrA

000 0011

TIMER2 : TINT2L

010 0011

VP2EVTYB

000 0100

TIMER2 : TINT2H

010 0100

VP2EVTCbB

000 0101

TIMER3 : TINT3L

010 0101

VP2EVTCrB

000 0110

TIMER3 : TINT3H

010 0110

VP3EVTYA

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