LAN9312 datasheet(263/458 Pages) SMSC

263 / 458 page

High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface

Datasheet

SMSC LAN9312

263

Revision 1.2 (04-08-08)

DATASHEET

Note 14.47

The default value of this field is determined by the configuration strap auto_mdix_strap_2.

See Section 4.2.4, "Configuration Straps," on page 40 for more information.

Note 14.48

The default value of this field is determined by the configuration strap auto_mdix_strap_1.

See Section 4.2.4, "Configuration Straps," on page 40 for more information.

11:1

RESERVED

Soft Reset (SRST)

Writing 1 generates a software initiated reset to the Host Bus Interface, the

Host MAC, and System CSR’s below address 100h. The System CSR’s are

all reset except for any NASR bits. Soft reset also clears any TX or RX

errors in the Host MAC transmitter and receiver (TXE/RXE). This bit is self-

clearing. In order to reset all values, the Reset Control Register

(RESET_CTL) must be used.

Note:

This bit will read high during assertion of DIGITAL_RST in the

Reset Control Register (RESET_CTL). The LAN9312 must always

be read at least once after power-up or reset to ensure that write

operations function correctly.

R/W

BITS

DESCRIPTION

TYPE

DEFAULT

LAN9312 Datasheet(PDF) 263 Page - SMSC Corporation