LAN9312 datasheet(261/458 Pages) SMSC

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High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface

Datasheet

SMSC LAN9312

261

Revision 1.2 (04-08-08)

DATASHEET

14.2.9.3

Hardware Configuration Register (HW_CFG)

This register allows the configuration of various hardware features including TX/RX FIFO sizes, Host

MAC transmit threshold properties, and software reset. A detailed explanation of the allowable settings

for FIFO memory allocation can be found in Section 9.7.3, "FIFO Memory Allocation Configuration,"

on page 121.

Note:

This register can be polled while the LAN9312 is in the reset or not ready state (READY bit is

cleared).

Offset:

074h

Size:

32 bits

BITS

DESCRIPTION

TYPE

DEFAULT

31:28

RESERVED

Device Ready (READY)

When set, this bit indicates that the LAN9312 is ready to be accessed. Upon

power-up, nRST reset, soft reset, or digital reset, the host processor may

interrogate this field as an indication that the LAN9312 has stabilized and is

fully active.

This bit can cause an interrupt if enabled.

Note:

With the exception of the HW_CFG, PMT_CTRL, BYTE_TEST, and

RESET_CTL registers, read access to any internal resources is

forbidden while the READY bit is cleared. Writes to any address

are invalid until this bit is set.

Note:

This bit is identical to bit 0 of the Power Management Control

AMDIX_EN Strap State Port 2

This bit reflects the state of the auto_mdix_strap_2 strap that connects to

the PHY. The strap value is loaded with the level of the auto_mdix_strap_2

during reset and can be re-written by the EEPROM Loader. The strap value

can be overridden by bit 15 and 13 of the Port 2 PHY Special Control/Status

Indication Register (Section 14.4.2.10).

Note 14.47

AMDIX_EN Strap State Port 1

This bit reflects the state of the auto_mdix_strap_1 strap that connects to

the PHY. The strap value is loaded with the level of the auto_mdix_strap_1

during reset and can be re-written by the EEPROM Loader. The strap value

can be overridden by bit 15 and 13 of the Port 1 PHY Special Control/Status

Indication Register (Section 14.4.2.10).

Note 14.48

24:22

RESERVED

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