LAN9312 datasheet(258/458 Pages) SMSC

258 / 458 page

High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface

Datasheet

Revision 1.2 (04-08-08)

258

SMSC LAN9312

DATASHEET

Note 14.42

The reserved bits 31-16 are used to pad the register to 32-bits so that each register is on

a DWORD boundary. When accessed serially (through the MII management protocol), the

Note 14.43

The default value of this field is the result of the Auto-Negotiation process if the Auto-

N ego tiatio n (VPHY_AN) b i t o f th e V i rtu a l PHY Ba si c C ontrol R egi ste r

(VPHY_BASIC_CTRL) is set. Otherwise, this field reflects the Speed Select LSB

(VPHY_SPEED_SEL_LSB) and Duplex Mode (VPHY_DUPLEX) bit settings of the

VPHY_BASIC_CTRL register. Refer to Section 7.3.1, "Virtual PHY Auto-Negotiation," on

page 96 for information on the Auto-Negotiation determination process of the Virtual PHY.

Note 14.44

the Reset Control Register (RESET_CTL) or Power Management Control Register

(PMT_CTRL). The NASR designation is only applicable when the Reset (VPHY_RST) bit

of the Virtual PHY Basic Control Register (VPHY_BASIC_CTRL) is set.

Note 14.45

The default value of this field is determined via the SQE_test_disable_strap_mii

configuration strap. Refer to Section 4.2.4, "Configuration Straps," on page 40 for

additional information.

LAN9312 Datasheet(PDF) 258 Page - SMSC Corporation