LAN9312 datasheet(322/458 Pages) SMSC

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High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface

Datasheet

Revision 1.2 (04-08-08)

322

SMSC LAN9312

DATASHEET

14.5.1.4

Switch Global Interrupt Pending Register (SW_IPR)

This read-only register contains the pending global interrupts for the switch fabric. A set bit indicates

an unmasked bit in the corresponding switch fabric sub-system has been triggered. All switch related

interrupts in this register may be masked via the Switch Global Interrupt Mask Register (SW_IMR)

the SWITCH_INT bit in the Interrupt Status Register (INT_STS). Refer to Chapter 5, "System

Interrupts," on page 49 for more information.

0005h

Size:

32 bits

BITS

DESCRIPTION

TYPE

DEFAULT

31:7

RESERVED

Buffer Manager Interrupt (BM)

Set when any unmasked bit in the Buffer Manager Interrupt Pending

Switch Engine Interrupt (SWE)

Set when any unmasked bit in the Switch Engine Interrupt Pending Register

(SWE_IPR) is triggered. This bit is cleared upon a read.

4:3

RESERVED

Port 2 MAC Interrupt (MAC_2)

Set when any unmasked bit in the MAC_IPR_2 register (see Section

14.5.2.44, on page 366) is triggered. This bit is cleared upon a read.

Port 1 MAC Interrupt (MAC_1)

Set when any unmasked bit in the MAC_IPR_1 register (see Section

14.5.2.44, on page 366) is triggered. This bit is cleared upon a read.

Port 0 MAC Interrupt (MAC_MII)

Set when any unmasked bit in the MAC_IPR_MII register (see Section

14.5.2.44, on page 366) is triggered. This bit is cleared upon a read.

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