LAN9312 datasheet(323/458 Pages) SMSC

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High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface

Datasheet

SMSC LAN9312

323

Revision 1.2 (04-08-08)

DATASHEET

14.5.2

Switch Port 0, Port 1, and Port 2 CSRs

This section details the switch Port 0(Host MAC), Port 1, and Port 2 CSRs. Each port provides a

functionally identical set of registers which allow for the configuration of port settings, interrupts, and

the monitoring of the various packet counters.

Because the Port 0, Port 1, and Port 2 CSRs are functionally identical, their register descriptions have

been consolidated. A lowercase “x” has been appended to the end of each switch port register name

in this section, where “x” should be replaced with “MII”, “1”, or “2” for the Port 0, Port 1, or Port 2

registers respectively. A list of the Switch Port 0, Port 1, and Port 2 registers and their corresponding

14.5.2.1

Port x MAC Version ID Register (MAC_VER_ID_x)

This read-only register contains switch device ID information, including the device type, chip version

and revision codes.

Port0: 0400h

Size:

32 bits

Port1: 0800h

Port2: 0C00h

BITS

DESCRIPTION

TYPE

DEFAULT

31:12

RESERVED

11:8

Device Type Code (DEVICE_TYPE)

7:4

Chip Version Code (CHIP_VERSION)

3:0

Revision Code (REVISION)

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