LAN9312 datasheet(321/458 Pages) SMSC

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High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface

Datasheet

SMSC LAN9312

321

Revision 1.2 (04-08-08)

DATASHEET

14.5.1.3

Switch Global Interrupt Mask Register (SW_IMR)

This read/write register contains the global interrupt mask for the switch fabric interrupts. All switch

related interrupts in the Switch Global Interrupt Pending Register (SW_IPR) may be masked via this

unmask the interrupt. When an unmasked switch fabric interrupt is generated in the Switch Global

Interrupt Pending Register (SW_IPR), the interrupt will trigger the SWITCH_INT bit in the Interrupt

Status Register (INT_STS). Refer to Chapter 5, "System Interrupts," on page 49 for more information.

0004h

Size:

32 bits

BITS

DESCRIPTION

TYPE

DEFAULT

31:9

RESERVED

8:7

RESERVED

Note:

These bits must be written as 11b

R/W

11b

Buffer Manager Interrupt Mask (BM)

When set, prevents the generation of switch fabric interrupts due to the

Buffer Manager via the Buffer Manager Interrupt Pending Register

(BM_IPR). The status bits in the SW_IPR register are not affected.

R/W

Switch Engine Interrupt Mask (SWE)

When set, prevents the generation of switch fabric interrupts due to the

Switch Engine via the Switch Engine Interrupt Pending Register (SWE_IPR).

The status bits in the SW_IPR register are not affected.

R/W

4:3

RESERVED

Note:

These bits must be written as 11b

R/W

11b

Port 2 MAC Interrupt Mask (MAC_2)

When set, prevents the generation of switch fabric interrupts due to the Port

2 MAC via the MAC_IPR_2 register (see Section 14.5.2.44, on page 366).

The status bits in the SW_IPR register are not affected.

R/W

Port 1 MAC Interrupt Mask (MAC_1)

When set, prevents the generation of switch fabric interrupts due to the Port

1 MAC via the MAC_IPR_1 register (see Section 14.5.2.44, on page 366).

The status bits in the SW_IPR register are not affected.

R/W

Port 0 MAC Interrupt Mask (MAC_MII)

When set, prevents the generation of switch fabric interrupts due to the Port

0 MAC via the MAC_IPR_MII register (see Section 14.5.2.44, on page 366).

The status bits in the SW_IPR register are not affected.

R/W

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