M58LW032C datasheet(16/61 Pages) STMICROELECTRONICS

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M58LW032C

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CONFIGURATION REGISTER

The Configuration Register is used to configure

the type of bus access that the memory will per-

form. The Configuration Register bits are de-

scribed in Table 3. They specify the selection of

the burst length, burst type, burst X and Y laten-

cies and the Read operation. See figures 6 and 7

for examples of Synchronous Burst Read configu-

rations.

The Configuration Register is set through the

Command Interface and will retain its information

until it is re-configured, the device is reset, or the

device goes into Reset/Power-Down mode. The

Configuration Register is read using the Read

Electronic Signature Command at address 05h.

Read Select Bit (CR15). The Read Select bit,

CR15, is used to switch between asynchronous

and synchronous Bus Read operations. When the

Read Select bit is set to ’1’, Bus Read operations

are asynchronous; when the Read Select but is

set to ’0’, Bus Read operations are synchronous.

On reset or power-up the Read Select bit is set to

’1’ for asynchronous access.

X-Latency Bits (CR13-CR11). The

X-Latency

bits are used during Synchronous Bus Read oper-

ations to set the number of clock cycles between

the address being latched and the first data be-

coming available. For correct operation the X-La-

tency bits can only assume the values in Table 3,

Configuration Register.

Internal Clock Divider Bit (CR10). The Internal

Clock Divider Bit is used to divide the internal clock

by two. When CR10 is set to ‘1’ the internal clock

is divided by two, which effectively means that the

X and Y-Latency values are multiplied by two, that

is the number of clock cycles between the address

being latched and the first data becoming avail-

able will be twice the value set in CR13-CR11, and

the number of clock cycles between consecutive

reads will be twice the value set in CR9. For exam-

ple 8-1-1-1 will become 16-2-2-2. When CR10 is

set to ‘0’ the internal clock runs normally and the X

and Y-Latency values are those set in CR13-CR11

and CR9.

Y-Latency Bit (CR9). The Y-Latency bit is used

during Synchronous Bus Read operations to set

the number of clock cycles between consecutive

reads. The Y-Latency value depends on both the

X-Latency value and the setting in CR9.

When the Y-Latency is 1 the data changes each

clock cycle; when the Y-Latency is 2 the data

changes every second clock cycle. See Table 3,

Configuration Register for valid combinations of

the Y-Latency, the X-Latency and the Clock fre-

quency.

Valid Data Ready Bit (CR8). The

Valid

Data

Ready bit controls the timing of the Valid Data

Ready output pin, R. When the Valid Data Ready

bit is ’0’ the Valid Data Ready output pin is driven

Low for the active clock edge when invalid data is

output on the bus. When the Valid Data Ready bit

is ’1’ the Valid Data Ready output pin is driven Low

one clock cycle prior to invalid data being output

on the bus.

Burst Type Bit (CR7). The Burst Type bit is used

to configure the sequence of addresses read as

sequential or interleaved. When the Burst Type bit

is ’0’ the memory outputs from interleaved ad-

dresses; when the Burst Type bit is ’1’ the memory

outputs from sequential addresses. See Tables 4,

Burst Type Definition, for the sequence of ad-

dresses output from a given starting address in

each mode.

Valid Clock Edge Bit (CR6). The

Valid

Clock

Edge bit, CR6, is used to configure the active edge

of the Clock, K, during Synchronous Burst Read

operations. When the Valid Clock Edge bit is ’0’

the falling edge of the Clock is the active edge;

when the Valid Clock Edge bit is ’1’ the rising edge

of the Clock is active.

Burst Length Bit (CR2-CR0). The Burst Length

bits set the maximum number of Words that can

be output during a Synchronous Burst Read oper-

ation.

Table 3, Configuration Register gives the valid

combinations of the Burst Length bits that the

memory accepts; Tables 4, Burst Type Definition,

give the sequence of addresses output from a giv-

en starting address for each length.

CR5 CR4 and CR3 are reserved for future use.

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