M58LW032C datasheet(20/61 Pages) STMICROELECTRONICS

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M58LW032C

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COMMAND INTERFACE

All Bus Write operations to the memory are inter-

preted by the Command Interface. Commands

consist of one or more sequential Bus Write oper-

ations. The Commands are summarized in Table

5, Commands. Refer to Table 5 in conjunction with

the text descriptions below.

After power-up or a Reset operation the memory

enters Read mode.

Synchronous Read operations and Latch Con-

trolled Bus Read operations can only be used to

read the memory array. The Electronic Signature,

CFI or Status Register will be read in asynchro-

nous mode or single synchronous burst mode.

Once the memory returns to Read Memory Array

mode the bus will resume the setting in the Config-

uration Register automatically.

Read Memory Array Command. The Read Mem-

ory Array command returns the memory to Read

mode. One Bus Write cycle is required to issue the

Read Memory Array command and return the

memory to Read mode. Once the command is is-

sued the memory remains in Read mode until an-

other command is issued. From Read mode Bus

Read commands will access the memory array.

While the Program/Erase Controller is executing a

Program, Erase, Block Protect, Blocks Unprotect

or Protection Register Program operation the

memory will not accept the Read Memory Array

command until the operation completes.

Read Electronic Signature Command. The Read

Electronic Signature command is used to read the

Manufacturer Code, the Device Code, the Block

Protection Status, the Configuration Register and

the Protection Register. One Bus Write cycle is re-

quired to issue the Read Electronic Signature

command. Once the command is issued subse-

quent Bus Read operations read the Manufacturer

Code, the Device Code, the Block Protection Sta-

tus, the Configuration Register or the Protection

Table 7, Read Electronic Signature, Table 8, Read

Protection Register and Figure 8, Protection Reg-

ister Memory Map for information on the address-

es.

Read Query Command. The Read Query Com-

mand is used to read data from the Common Flash

Interface (CFI) Memory Area. One Bus Write cycle

is required to issue the Read Query Command.

Once the command is issued subsequent Bus

Read operations read from the Common Flash In-

terface Memory Area. See Appendix B, Tables 26,

27, 28, 29, 30 and 31 for details on the information

contained in the Common Flash Interface (CFI)

memory area.

Read Status Register Command. The Read Sta-

tus Register command is used to read the Status

the Read Status Register command. Once the

command is issued subsequent Bus Read opera-

tions read the Status Register until another com-

mand is issued.

The Status Register information is present on the

output data bus (DQ1-DQ7) when both Chip En-

able and Output Enable are low, VIL.

See the section on the Status Register and Table

10 for details on the definitions of the Status Reg-

ister bits

Clear Status Register Command. The Clear Sta-

tus Register command can be used to reset bits

SR1, SR3, SR4 and SR5 in the Status Register to

‘0’. One Bus Write is required to issue the Clear

Status Register command.

The bits in the Status Register are sticky and do

not automatically return to ‘0’ when a new Write to

Buffer and Program, Erase, Block Protect, Block

Unprotect or Protection Register Program com-

mand is issued. If any error occurs then it is essen-

tial to clear any error bits in the Status Register by

issuing the Clear Status Register command before

attempting a new Program, Erase or Resume

command.

Block Erase Command. The Block Erase com-

mand can be used to erase a block. It sets all of

the bits in the block to ‘1’. All previous data in the

block is lost. If the block is protected then the

Erase operation will abort, the data in the block will

not be changed and the Status Register will output

the error.

Two Bus Write operations are required to issue the

command; the second Bus Write cycle latches the

block address in the internal state machine and

starts the Program/Erase Controller. Once the

command is issued subsequent Bus Read opera-

tions read the Status Register. See the section on

the Status Register for details on the definitions of

the Status Register bits.

During the Erase operation the memory will only

accept the Read Status Register command and

the Program/Erase Suspend command. All other

commands will be ignored. Typical Erase times

are given in Table 9.

See Appendix C, Figure 25, Block Erase Flow-

chart and Pseudo Code, for a suggested flowchart

on using the Block Erase command.

Word Program Command. The Word Program

command is used to program a single word in the

memory array. Two Bus Write operations are re-

quired to issue the command; the first write cycle

sets up the Word Program command, the second

write cycle latches the address and data to be pro-

grammed in the internal state machine and starts

the Program/Erase Controller.

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