M58LW032C datasheet(22/61 Pages) STMICROELECTRONICS

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M58LW032C

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Read mode and the valid Clock edge configura-

tion.

Two Bus Write cycles are required to issue the Set

Configuration Register command. Once the com-

mand is issued the memory returns to Read mode

as if a Read Memory Array command had been is-

sued.

The value for the Configuration Register is pre-

sented on A1-A16. CR0 is on A1, CR1 on A2, etc.;

the other address bits are ignored.

Block Protect Command. The

Block

Protect

command is used to protect a block and prevent

Program or Erase operations from changing the

data in it. Two Bus Write cycles are required to is-

sue the Block Protect command; the second Bus

Write cycle latches the block address in the inter-

nal state machine and starts the Program/Erase

Controller. Once the command is issued subse-

quent Bus Read operations read the Status Reg-

ister. See the section on the Status Register for

details on the definitions of the Status Register

bits.

During the Block Protect operation the memory will

only accept the Read Status Register command.

All other commands will be ignored. Typical Block

Protection times are given in Table 9.

The Block Protection bits are non-volatile, once

set they remain set through reset and power-

down/power-up. They are cleared by a Blocks Un-

protect command.

See Appendix C, Figure 27, Block Protect Flow-

chart and Pseudo Code, for a suggested flowchart

on using the Block Protect command.

Blocks Unprotect Command. The Blocks Un-

protect command is used to unprotect all of the

blocks. Two Bus Write cycles are required to issue

the Blocks Unprotect command; the second Bus

Write cycle starts the Program/Erase Controller.

Once the command is issued subsequent Bus

Read operations read the Status Register. See the

section on the Status Register for details on the

definitions of the Status Register bits.

During the Block Unprotect operation the memory

will only accept the Read Status Register com-

mand. All other commands will be ignored. Typical

Block Protection times are given in Table 9.

See Appendix C, Figure 28, Block Unprotect Flow-

chart and Pseudo Code, for a suggested flowchart

on using the Block Unprotect command.

Protection Register Program Command. The

Protection Register Program command is used to

Program the 64 bit user segment of the Protection

time. Two write cycles are required to issue the

Protection Register Program command.

The first bus cycle sets up the Protection

The second latches the Address and the Data to

be written to the Protection Register and starts

the Program/Erase Controller.

Read operations output the Status Register con-

tent after the programming has started.

The user-programmable segment can be locked

by programming bit 1 of the Protection Register

Lock location to ‘0’ (see Table 8). Bit 0 of the Pro-

tection Register Lock location locks the factory

programmed segment and is programmed to ‘0’ in

the factory. The locking of the Protection Register

is not reversible, once the lock bits are pro-

grammed no further changes can be made to the

values stored in the Protection Register, see Fig-

ure 8, Protection Register Memory Map. Attempt-

ing to program a previously protected Protection

The Protection Register Program cannot be sus-

pended. See Appendix C, Figure 29, Protection

for the flowchart for using the Protection Register

Program command.

Configure STS Command.

The Configure STS command is used to configure

the Status/(Ready/Busy) pin. After power-up or re-

set the STS pin is configured in Ready/Busy

mode. The pin can be configured in Status mode

using the Configure STS command (refer to Sta-

tus/(Ready/Busy) section for more details.

Two write cycles are required to issue the Config-

ure STS command.

The first bus cycle sets up the Configure STS

command.

The second specifies one of the four possible

configurations (refer to Table 6, Configuration

Codes):

– Ready/Busy mode

– Pulse on Erase complete mode

– Pulse on Program complete mode

– Pulse on Erase or Program complete mode

The device will not accept the Configure STS com-

mand while the Program/Erase controller is busy

or during Program/Erase Suspend. When STS pin

is pulsing it remains Low for a typical time of

250ns. Any invalid Configuration Code will set an

error in the Status Register.

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