M58MR016C datasheet(14/51 Pages) STMICROELECTRONICS

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Table 12. Status Register Bits

Note: Logic level ’1’ is VIH and ’0’ is VIL.

Mnemonic

Bit

Name

Logic

Level

Definition

Note

P/ECS

Status

Ready

Indicates the P/E.C. status, check during

Program or Erase, and on completion before

checking bits b4 or b5 for Program or Erase

Success.

Busy

ESS

Erase

Suspend

Status

Suspended

On an Erase Suspend instruction P/ECS and

ESS bits are set to ’1’. ESS bit remains ’1’ until

an Erase Resume instruction is given.

In Progress or

Completed

Erase

Status

Erase Error

ES bit is set to ’1’ if P/E.C. has applied the

maximum number of erase pulses to the block

without achieving an erase verify.

Erase Success

Program

Status

Program Error

PS bit set to ’1’ if the P/E.C. has failed to

program a word.

Program

Success

VPPS

VPP Status

VPP Invalid,

Abort

VPPS bit is set if the VPP voltage is below

VPPLK when a Program or Erase instruction is

executed. VPP is sampled only at the beginning

of the erase/program operation.

VPP OK

PSS

Program

Suspend

Status

Suspended

On a program Suspend instruction P/ECS and

PSS bits are set to ’1’. PSS remains ’1’ until a

Program Resume Instruction is given.

In Progress or

Completed

BPS

Block

Protection

Status

Program/Erase

on protected

Block, Abort

BPS bit is set to ’1’ if a Program or Erase

operation has been attempted on a protected

block.

No operation to

protected blocks

Reserved

must be issued to reset b5, b4, b3 and b1 of the

Status Register.

During the execution of the program by the P/E.C.,

the bank in programming accepts only the RSR

(Read Status Register) and PES (Program/Erase

Suspend) instructions. See Figure 16 for Program

Flowchart and Pseudo Code.

Double Word Program (DPG)

This feature is offered to improve the programming

throughput, writing a page of two adjacent words

in parallel. The first command must be given to the

target block and only one partition can be pro-

grammed at a time; the other partition must be in

one of the read modes or in the erase suspended

mode (see Table 8).

The two words must differ only for the address A0.

Programming should not be attempted when VPP

is not at VPPH. The operation can also be executed

if VPP is below VPPH but result could be uncertain.

These instruction uses three write cycles. The first

command written is the Double Word Program

Set-Up command 30h. A second write operation

latches the Address and the Data of the first word

to be written, the third write operation latches the

Address and the Data of the second word to be

written and starts the P/E.C. (see Table 11).

Read operations in the targeted bank output the

Status Register content after the programming

has started. The Status Register bit b7 returns ’0’

while the programming is in progress and ’1’ when

it has completed. After completion the Status reg-

ister bit b4 returns ’1’ if there has been a Program

Failure. Status register bit b1 returns ’1’ if the user

is attempting to program a protected block. Status

Any attempt to write a ’1’ to an already pro-

grammed bit will result in a program fail (status

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