M58MR016C datasheet(4/51 Pages) STMICROELECTRONICS

4 / 51 page

M58MR016C, M58MR016D

4/51

The architecture includes a 128 bit Protection reg-

ister that is divided into two 64 bit segments. In the

first one is written a unique device number, while

the second one is programmable by the user. The

user programmable segment can be permanently

protected programming the bit 1 of the Protection

Lock Register (see protection register and Securi-

ty Block). The parameter block (# 0) is a security

block. It can be permanently protected by the user

programming the bit 2 of the Protection Lock Reg-

ister.

Block protection against Program or Erase pro-

vides additional data security. All blocks are pro-

tected and unlocked at Power-up. Instructions are

provided to protect or un-protect any block in the

application. A second register locks the protection

status while WP is low (see Block Locking descrip-

tion).

Table 3. Bank Size and Sectorization

Bank Size

Parameter Blocks

Main Blocks

Bank A

4 Mbit

8 blocks of 4 KWord

7 blocks of 32 KWord

Bank B

12 Mbit

24 blocks of 32 KWord

Figure 3. Memory Map

AI05230

512 Kbit or

32 KWord

000000h

007FFFh

512 Kbit or

32 KWord

0F0000h

0F7FFFh

Top Boot Block

Address lines A19-A0

512 Kbit or

32 KWord

0B8000h

0BFFFFh

Total of 24

Main Blocks

512 Kbit or

32 KWord

0C0000h

0C7FFFh

64 Kbit or

4 KWord

0FF000h

0FFFFFh

64 Kbit or

4 KWord

0F8000h

0F8FFFh

Total of 7

Main Blocks

Total of 8

Parameter

Blocks

Bank B

Bank A

64 Kbit or

4 KWord

000000h

000FFFh

512 Kbit or

32 KWord

038000h

03FFFFh

Bottom Boot Block

Address lines A19-A0

64 Kbit or

4 KWord

007000h

007FFFh

Total of 8

Parameter

Blocks

512 Kbit or

32 KWord

008000h

00FFFFh

512 Kbit or

32 KWord

0F8000h

0FFFFFh

512 Kbit or

32 KWord

040000h

047FFFh

Total of 7

Main Blocks

Total of 24

Main Blocks

Bank B

Bank A

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