M68Z512 datasheet(2/12 Pages) STMICROELECTRONICS

2 / 12 page

M68Z512

2/12

Figure 2. TSOP Connections

DQ5

DQ6

DQ7

DQ0

VSS

DQ3

DQ4

DQ1

DQ2

A12

A15

A14

A16

A17

A10

A11

A13

AI03031

M68Z512

VCC

A18

Table 2. Absolute Maximum Ratings (1)

Note: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may

cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions

above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi-

tions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant qual-

ity documents.

2. Up to a maximum operating VCC of 5.5V only.

3. One output at a time, not to exceed 1 second duration.

Symbol

Parameter

Value

Unit

Ambient Operating Temperature

0 to 70

°C

TSTG

Storage Temperature

–65 to 150

°C

VIO

(2)

Input or Output Voltage

–0.3 to VCC + 0.3

VCC

Supply Voltage

–0.3 to 7.0

(3)

Output Current

Power Dissipation

READ MODE

The M68Z512 is in the Read mode whenever

Write Enable (W) is High with Output Enable (G)

Low, and Chip Enable (E) is asserted. This pro-

vides access to data from eight of the 4,194,304

locations in the static memory array, specified by

the 19 address inputs. Valid data will be available

at the eight output pins within tAVQV after the last

stable address, providing G is Low and E is Low.

If Chip Enable or Output Enable access times are

not met, data access will be measured from the

limiting parameter (tELQV or tGLQV) rather than the

address. Data out may be indeterminate at tELQX

and tGLQX, but data lines will always be valid at

tAVQV.

WRITE MODE

The M68Z512 is in the Write mode whenever the

W and E pins are Low. Either the Chip Enable in-

put (E) or the Write Enable input (W) must be de-

asserted during Address transitions for subse-

quent write cycles. Write begins with the concur-

rence of Chip Enable being active with W low.

Therefore, address setup time is referenced to

Write Enable and Chip Enable as tAVWL and tAVEH

respectively, and is determined by the latter occur-

ring edge.

The Write cycle can be terminated by the earlier

rising edge of E, or W.

if the Output is enabled (E = Low and G = Low),

then W will return the outputs to high impedance

within tWLQZ of its falling edge. Care must be taken

to avoid bus contention in this type of operation.

Data input must be valid for tDVWH before the ris-

ing edge of Write Enable, or for tDVEH before the

rising edge of E, whichever occurs first, and re-

main valid for tWHDX or tEHDX.

M68Z512 Datasheet(PDF) 2 Page - STMicroelectronics

M68Z512 Datasheet(HTML) 2 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12

Datasheet Download

Link URL