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M68Z512

OPERATIONAL MODE

The M68Z512 has a Chip Enable power down fea-

ture which invokes an automatic standby mode

whenever Chip Enable is de-asserted (E = High).

An Output Enable (G) signal provides a high

speed tri-state control, allowing fast read/write cy-

cles to be achieved with the common I/O data bus.

Operational modes are determined by device con-

trol inputs W and E as summarized in the Operat-

ing Modes table.

Table 3. Operating Modes

Operation

E

W

G

DQ0-DQ7

Power

Read

Hi-Z

Active

Read

Data Output

Active

Write

X

Data Input

Active

Deselect

X

X

Hi-Z

Standby

Table 4. AC Measurement Conditions

Note: Output Hi-Z is defined as the point where data is no longer

driven.

Input Rise and Fall Times

≤ 5ns

Input Pulse Voltages

0 to 3V

Input and Output Timing Ref. Voltages

1.5V

Figure 3. AC Testing Load Circuit

AI03032

5.0V

OUT

CL = 100pF or 5pF

CL includes JIG capacitance

1838

Ω

DEVICE

UNDER

TEST

994

Ω

Note: 1. Sampled only, not 100% tested.

2. Outputs deselected.

Symbol

Parameter

Test Condition

Min

Max

Unit

Input Capacitance on all pins (except DQ)

6pF

(2)

Output Capacitance

8pF