AS3953 datasheet(50/71 Pages) AMSOSRAM

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ams Datasheet

Page 49

[v1-05] 2019-Feb-15

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AS3953A − Detailed Description

Mode Definition Registers

Figure 55:

Mode Definition Register

Note(s):

1. Default value is loaded from EEPROM configuration word bits

b12 to b7 during power-up initialization.

Address# 01h : Mode Definition

Type: RW

Bit

Name

Default

Function

Comments

7RFU

6RFU

r_mod_1

See note (1)

00: ISO 14443A Level-4 Protocol

mode

01: ISO 14443A Level-3 Protocol

mode

10: Framing mode

11: Transparent mode

ISO mode in case of register

control;

If ISO 14443A Protocol mode

is selected through registers,

logic is forced in Level-4

mode.

r_mod_2

See note (1)

r_rxncrc

See note (1)

1: Rx – CRC is not checked, CRC

part of message is also put in

FIFO

Applicable in ISO 14443A

Level-3 Protocol mode and

Framing mode. In Protocol

mode, applicable for frames

which are put in FIFO.

r_rxbs

See note (1)

1: Rx – Bit stream mode,

received bits are put in FIFO (no

parity and CRC check)

r_txncrc

See note (1)

1: Tx – Do not generate CRC

r_txbs

See note (1)

1: Tx – Bit stream mode, bits put

in FIFO are sent without parity

and CRC generation

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