AS3953 datasheet(57/71 Pages) AMSOSRAM

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[v1-05] 2019-Feb-15

AS3953A − Detailed Description

Figure 63:

Auxiliary Interrupt Register

Notes:

1. At power-up and after Set Default command content of this register is set to 0.

2. After Auxiliary Interrupt Register has been read its content is set to 0.

Figure 64:

FIFO Status Register 1

Note(s):

1. At power-up and after direct commands Set Default and Clear content of this register is set to 0.

Address# 0Bh : Auxiliary Interrupt

Type: R

Bit

Name

Function

Comments

7I_des

IRQ due to reception of DESELECT

command

6I_er_fr

Framing error

I_er_par

Parity error

In case of parity or/and CRC error

the receive data is still put in FIFO,

error IRQ is additionally send.

I_er_crc

CRC error

I_er_fifo

FIFO error (overflow/underflow)

See FIFO Status Register 2

2I_eew

IRQ due to successful termination of

EEPROM programming

In case EEPROM Write command

was sent through SPI

I_er_eew

Error during EEPROM programming

(writing to write protected word,

writing to nonexistent address)

In case EEPROM Write command

was sent through SPI

I_ee_spi

IRQ due to interruption of EEPROM

access due to PICC interface activation

Address# 0Ch: FIFO Status 1

Type: R

Bit

Name

Function

Comments

7RFU

6RFU

5fifo_b5

Number of data bytes (binary coded) in

the FIFO which were not read out

Valid range is from 000000 to

100000

000000 means that there are no

data bytes to be read out

4fifo_b4

3fifo_b3

2fifo_b2

1fifo_b1

0fifo_b0

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