AS3953 datasheet(58/71 Pages) AMSOSRAM

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ams Datasheet

Page 57

[v1-05] 2019-Feb-15

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AS3953A − Detailed Description

Figure 65:

FIFO Status Register 2

Note(s):

1. At power-up and after direct commands Set Default and Clear content of this register is set to 0

Definition of Number of Transmitted Bytes

Figure 66:Number of Transmitted Bytes Register 1

Note(s):

1. Default setting is set at power-up and after Set Default command.

Address# 0Dh: FIFO Status 2

Type: R

Bit

Name

Function

Comments

7RFU

fifo_unf

FIFO underflow

Set when more bytes than the

actual content of FIFO are read

fifo_ovr

FIFO overflow

fifo_ncp

Last FIFO byte is not complete

3fifo_lb2

Number of bits in last FIFO byte in case

it was not complete (fifo_npc=1)

MSB bits valid

2fifo_lb1

1fifo_lb0

np_lb

Parity bit is missing in last byte

This is a framing error

Address# 10h: Number of Transmitted Bytes 1

Type: RW

Bit

Name

Default

Function

Comments

7RFU

Number of full bytes to be

transmitted in one

command, MSB bits

Maximum supported number of

bytes is 1023

6RFU

5RFU

4ntx9

3ntx8

2ntx7

1ntx6

0ntx5

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