RX72N datasheet(144/179 Pages) RENESAS

144 / 179 page

R01DS0343EJ0120 Rev.1.20

Page 144 of 179

Nov 15, 2023

RX72N Group

2. Electrical Characteristics

2.4.7.16

SDHI

Note 1. We recommend using pin names that have a letter (“-A”, “-B”, etc.) to indicate group membership per group in the test.

For the SDHI, the AC portion of the electrical characteristics is measured per group.

Figure 2.80

SD Host Interface Input/Output Signal Timing

Table 2.45

SDHI Timing

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6V, 2.7V ≤ VREFH0 ≤ AVCC0,

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0V,

PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, Ta = Topr,

Output load conditions: VOH = 0.5 × VCC, VOL = 0.5 × VCC, C = 30pF

High-drive output is selected by the drive capacity control register.

Item

Symbol

Min.

Max.

Unit

Test

Conditions

SDHI

SDHI_CLK output cycle time

tPP(SD)

—

Figure 2.80

SDHI_CLK output width at high level

tWH(SD)

0.4 × tPP(SD)

—ns

SDHI_CLK output width at low level

tWL(SD)

0.4 × tPP(SD)

—ns

SDHI_CLK output rising time

tTLH(SD)

—3

SDHI_CLK output falling time

tTHL(SD)

—3

SDHI_CMD, SDHI_D3 to SDHI_D0 output data delay (data

transfer mode)

tODLY(SD)

–6.5

SDHI_CMD, SDHI_D3 to SDHI_D0 input data setup time

tISU(SD)

6—

SDHI_CMD, SDHI_D3 to SDHI_D0 input data hold time

tIH(SD)

2—

SDHI_CLK output

SDHI_CMD, SDHI_D3 to SDHI_D0 input

SDHI_CMD, SDHI_D3 to SDHI_D0 output

tWL(SD)

tWH(SD)

tPP(SD)

tISU(SD) tIH(SD)

tTLH(SD)

tTHL(SD)

tODLY(SD)

VIH

50% VCC

VIH

50% VCC

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