RX72N datasheet(145/179 Pages) RENESAS

145 / 179 page

R01DS0343EJ0120 Rev.1.20

Page 145 of 179

Nov 15, 2023

RX72N Group

2. Electrical Characteristics

2.4.7.17

ETHERC

n = 0, 1

Note 1. RMIIn_TXD_EN, RMIIn_TXD1, RMIIn_TXD0

Note 2. RMIIn_CRS_DV, RMIIn_RXD1, RMIIn_RXD0, RMIIn_RX_ER

Table 2.46

ETHERC Timing

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, Ta = Topr,

Output load conditions: VOH = 0.5 × VCC, VOL = 0.5 × VCC, C = 30 pF,

RMII: High-drive output for the high-speed interface is selected in the drive capacity control register.

MII: High-drive output is selected by the drive capacity control register.

Item

Symbol

Min.

Max.

Unit

Test

Conditions

ETHERC

(RMII)

REF50CK cycle time

Tck

—

Figure 2.81 to

Figure 2.84

REF50CK frequency Typ. 50 MHz

—

50 + 100 ppm

MHz

REF50CK duty

—

REF50CK rise/fall time

Tckr/ckf

0.5

3.5

RMIIn_xxxx*1 output delay time

Tco

2.5

15.0

RMIIn_xxxx*2 setup time

Tsu

3—

RMIIn_xxxx*2 hold time

Thd

1—

RMIIn_xxxx*1, *2 rise/fall time

Tr/Tf

—5

ETn_WOL output delay time

tWOLd

23.5

Figure 2.85

ETHERC

(MII)

ETn_TX_CLK cycle time

tTcyc

—

ETn_TX_EN output delay time

tTENd

Figure 2.86

ETn_ETXD0 to ETn_ETXD3 output delay time

tMTDd

120

ETn_CRS setup time

tCRSs

—

ETn_CRS hold time

tCRSh

—

ETn_COL setup time

tCOLs

—

Figure 2.87

ETn_COL hold time

tCOLh

—

ETn_RX_CLK cycle time

tTRcyc

—

ETn_RX_DV setup time

tRDVs

—

Figure 2.88

ETn_RX_DV hold time

tRDVh

—

ETn_ERXD0 to ETn_ERXD3 setup time

tMRDs

—

ETn_ERXD0 to ETn_ERXD3 hold time

tMRDh

—

ETn_RX_ER setup time

tRERs

—

Figure 2.89

ETn_RX_ER hold time

tRERh

—

ETn_WOL output delay time

tWOLd

23.5

Figure 2.90

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