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9DBL0853ANDGI Datasheet(PDF) 1 Page - Renesas Technology Corp |
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9DBL0853ANDGI Datasheet(HTML) 1 Page - Renesas Technology Corp |
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1 / 32 page ![]() 1 ©2020 Renesas Electronics Corporation December 9, 2022 Description The 9DBL02x3/9DBL04x3/ 9DBL06x3/9DBL08x3 buffers are low-power, high-performance members of Renesas' full featured PCIe family. The buffers support PCIe Gen1–5 and provide a Loss of Signal (LOS) indicator. PCIe Clocking Architectures ▪ Common Clocked (CC) ▪ Independent Reference (IR) with/without SSC (SRIS, SRNS) Typical Applications ▪ PCIe Riser Cards ▪ nVME Storage ▪ Networking ▪ Accelerators ▪ Industrial Control/Embedded Key Specifications ▪ Additive PCIe Gen5 CC jitter < 60fs RMS (fanout mode) ▪ PCIe Gen5 CC jitter < 150fs RMS (High-BW ZDB Mode) Features ▪ LOS open-drain output indicates loss of input clock ▪ 2 to 8 Low-Power HCSL (LP-HCSL) outputs eliminate 4 resistors per output pair ▪ 9DBLxx4x devices provide integrated 100Ω terminations ▪ 9DBLxx5x devices provide integrated 85Ω terminations ▪ See AN-891 for easy coupling to other logic families ▪ Spread-spectrum compatible ▪ Dedicated OE# pin for each output ▪ 1MHz to 200MHz operation in fan-out mode ▪ 3 selectable SMBus addresses ▪ Extensive SMBus-selectable features allow optimization to customer requirements ▪ SMBus interface not required for device operation ▪ -40°C to +85°C operating temperature range ▪ Space-saving 4 × 4 mm 24-VFQFPN to 6 × 6 mm 48-VFQFPN packages (see Ordering Information table for details) Block Diagram DIFn# PLL CLK_IN CLK_IN# ^vHIBW_BYPM-LOBW# DIFn DIF0 DIF0# Control Logic ^CKPWRGD_PD# 2, 4, 6, 8 Outputs n = 1, 3, 5, 7 vOE[n:0]# SDATA_3.3 SCLK_3.3 Factory Configuration SMBus Engine vSADR_tri FB_DNC# FB_DNC# n+1 LOS LOS Logic 2 to 8-Output 3.3V PCIe Zero-Delay/Fanout Buffers with LOS 9DBL02x3/9DBL04x3/ 9DBL06x3/9DBL08x3 Datasheet |
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