9DBL0853ANDGI datasheet(13/32 Pages) RENESAS

13 / 32 page

December 9, 2022

9DBL02x3/9DBL04x3/ 9DBL06x3/9DBL08x3 Datasheet

Table 13. Input/Supply/Common Parameters – Recommended Operating Conditions

Symbol

Parameter

Conditions

Minimum Typical Maximum Units

VDDx

Supply Voltage

Supply voltage for core and analog.

3.135

3.3

3.465

VDDIO Output Supply Voltage [a]

[a] Only present on 9DBL06xx and 9DBL08xx devices.

Supply voltage for Low Power HCSL outputs.

0.95

1.05–3.3

3.465

TAMB

Ambient Operating Temperature Industrial range.

-40

°C

VIH

Input High Voltage

Single-ended inputs, except SMBus.

0.75 VDDx

VDDx + 0.3 V

VIL

Input Low Voltage

-0.3

0.25 VDDx

VIHtri

Input High Voltage

Single-ended tri-level inputs

('_tri' suffix).

0.75 VDDx

VDD + 0.3

VIMtri

Input Mid Voltage

0.4 VDDx 0.5 VDDx 0.6 VDDx

VILtri

Input Low Voltage

-0.3

0.25 VDDx

IIN

Single-ended Input Current

Inputs without internal pull-up/pull-down resistors

VIN = GND, VIN = VDD.

-5

μA

IINP

Inputs with internal pull-up resistors, VIN = 0V.

Inputs with internal pull-down resistors, VIN = VDD.

-50

μA

FIN

Input Frequency

Bypass Mode.

200

MHz

100MHz PLL Mode.

100.00

140

MHz

50MHz PLL Mode.

50.00

MHz

125MHz PLL Mode.

125.00

175

MHz

Lpin

Pin Inductance [b]

[b] Guaranteed by design and characterization, not 100% tested in production.

CIN

Capacitance [b]

Logic Inputs, except DIF_IN.

1.5

CINDIF_IN

DIF_IN differential clock inputs.

1.5

2.7

COUT

Output pin capacitance.

TSTAB Clk Stabilization [c]

[c] Control inputs must be monotonic from 20% to 80% of input swing.

From VDD Power-Up and after input clock

stabilization or deassertion of PD# to 1st clock.

fSSCMODIN Input SS Modulation Frequency

PCIe applications.

kHz

Non-PCIe applications.

kHz

tLATOE# OE# Latency [b] [c]

DIF start after OE# assertion

DIF stop after OE# deassertion.

clocks

tDRVPD Tdrive_PD# [b] [d]

[d] Time from deassertion until outputs are > 200 mV.

DIF output enable after PD# deassertion.

300

μs

Tfall [c]

Fall time of single-ended control inputs.

Trise [c]

Rise time of single-ended control inputs.

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