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AD5592R Datasheet(PDF) 3 Page - Analog Devices

Part # AD5592R
Description  8-Channel, 12-Bit, Configurable ADC/DAC with On-Chip Reference, SPI Interface
PDF  54 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD5592R Datasheet(HTML) 3 Page - Analog Devices

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Data Sheet
AD5592R
TABLE OF CONTENTS
analog.com
Rev. G | 3 of 54
Changes to Internal Reference Section......................................................................................................... 25
Changes to RESET Function Section............................................................................................................25
Changes to Temperature Indicator Section....................................................................................................25
Changes to Serial Interface Section.............................................................................................................. 26
Moved Table 10..............................................................................................................................................26
Changes to Read Mode Section.................................................................................................................... 27
Changes to Configuring the AD5592R/AD5592R-1 Section, Table 11, and Table 12....................................27
Changes to General-Purpose Control Register Section................................................................................ 29
Deleted Table 17 and Table 18...................................................................................................................... 29
Changes to DAC Write Operation Section.....................................................................................................29
Changes to LDAC Mode Operation Section.................................................................................................. 29
Deleted Table 19 to Table 22......................................................................................................................... 29
Changes to DAC Readback Section..............................................................................................................29
Deleted Table 23 and Table 24...................................................................................................................... 29
Changes to ADC Operation Section.............................................................................................................. 29
Moved Figure 45 to Figure 48........................................................................................................................30
Changes to Changing an ADC Sequence Section........................................................................................ 31
Deleted Table 25 to Table 29......................................................................................................................... 31
Added ADC Conversion Result Section.........................................................................................................32
Changes to Setting Pins as Outputs Section................................................................................................. 32
Changes to Setting Pins as Inputs Section....................................................................................................32
Moved Figure 50............................................................................................................................................ 32
Deleted Table 30 to Table 37......................................................................................................................... 32
Deleted Table 38 to Table 41......................................................................................................................... 33
Changes to Power-Down Mode Section........................................................................................................ 33
Deleted Table 42 and Table 43...................................................................................................................... 33
Changes to Reset Function Section.............................................................................................................. 33
Changes to Readback and LDAC Mode Register Section............................................................................ 33
Deleted Table 44 to Table 46......................................................................................................................... 33
Added Register Map Section......................................................................................................................... 35
Added Register Summary: AD5592R/AD5592R-1 Control Register Map Section........................................ 35
Moved Table 13..............................................................................................................................................35
Changes to Table 13......................................................................................................................................35
Added Register Details: AD5592R/AD5592R-1 Control Register Map Section.............................................35
Added NOP Register Section and Table 14...................................................................................................36
Added DAC Readback Register Section and Table 15..................................................................................36
Added ADC Sequence Register Section and Table 16..................................................................................37
Added General-Purpose Control Register Section and Table 17...................................................................38
Added ADC Pin Configuration Register Section and Table 18...................................................................... 39
Added DAC Pin Configuration Register Section and Table 19...................................................................... 40
Added Pull-Down Configuration Register Section and Table 20....................................................................41
Added Configuration Register Readback and LDAC Mode Register Section and Table 21.......................... 42
Added GPIO Write Configuration Register Section and Table 22..................................................................43
Added GPIO Write Data Register Section and Table 23................................................................................44
Added GPIO Read Configuration Register Section and Table 24..................................................................46
Added Power-Down/Reference Control Register Section and Table 25........................................................47
Added GPIO Open-Drain Configuration Register Section and Table 26........................................................48
Added Three-State Configuration Register Section and Table 27................................................................. 49
Added Software Reset Register Section and Table 28.................................................................................. 50



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