Data Sheet

AD7490

Rev. E | Page 3 of 28

SPECIFICATIONS

VDD = VDRIVE = 2.7 V to 5.25 V, REFIN = 2.5 V, SCLK frequency (fSCLK)1 = 20 MHz, TA = TMIN to TMAX, unless otherwise noted. Temperature

range: −40°C to +85°C (B Version), −40°C to +125°C (W Version).

Table 1.

Parameter

Test Conditions/Comments

AD7490B

AD7490W

Unit

Min

Typ

Max

Min

Typ

Max

DYNAMIC PERFORMANCE

fIN = 50 kHz sine wave,

fSCLK = 20 MHz

Signal-to-Noise-and-Distortion (SINAD)2

VDD = 5 V

69

70.5

66.5

68.8

dB

VDD = 3 V, fSCLK = 16 MHz

68

69.5

68

68.9

dB

Signal-to-Noise Ratio (SNR)2

69.5

67

68.8

dB

Total Harmonic Distortion (THD)2

VDD = 5 V

−84

−74

−78.6

−70

dB

VDD = 3 V, fSCLK = 16 MHz

−77

−71

−81.2

−71

dB

Peak Harmonic or Spurious Noise (SFDR)2

VDD = 5 V

−86

−75

−81.3

−73

dB

VDD = 3 V, fSCLK = 16 MHz

−80

−73

−83.1

−73

dB

Intermodulation Distortion (IMD)2

fa = 40.1 kHz, fb = 41.5 kHz

Second-Order Terms

−85

−85

dB

Third-Order Terms

−85

−85

dB

Aperture Delay

10

10

ns

Aperture Jitter

50

50

ps

Channel-to-Channel Isolation2

fIN = 400 kHz

−82

−82

dB

Full Power Bandwidth

3 dB

8.2

8.2

MHz

0.1 dB

1.6

1.6

MHz

DC ACCURACY2

Resolution

12

12

Bits

Integral Nonlinearity

−1

+1

−2

+2

LSB

Differential Nonlinearity

Guaranteed no missed codes to

12 bits

−0.95

+1.5

−0.95

+2

LSB

0 V to REFIN Input Range

Straight binary output coding

Offset Error

−8

±0.6

+8

−8

±0.6

+8

LSB

Offset Error Match

−0.5

+0.5

−1.5

+1.5

LSB

Gain Error

−2

+2

−3

+3

LSB

Gain Error Match

−0.6

+0.6

−1.5

+1.5

LSB

0 V to 2 × REFIN Input Range

−REFIN to +REFIN biased about

REFIN with twos complement

output coding offset

Positive Gain Error

−2

+2

−2.5

+2.5

LSB

Positive Gain Error Match

−0.5

+0.5

−1.4

+1.4

LSB

Zero Code Error

−8

±0.6

+8

−8

+8

LSB

Zero Code Error Match

−0.5

+0.5

−0.5

+0.5

LSB

Negative Gain Error

−1

+1

−2.5

+2.5

LSB

Negative Gain Error Match

−0.5

+0.5

−1.1

+1.1

LSB

ANALOG INPUT

V

Input Voltage Range

RANGE bit set to 1

0

REFIN

0

REFIN

RANGE bit set to 0, VDD = 4.75 V

to 5.25 V for 0 V to 2 × REFIN

0

2 ×

REFIN

0

2 ×

REFIN

V

DC Leakage Current

±1

±1

µA

Input Capacitance

20

20

pF

REFERENCE INPUT

REFIN Input Voltage

±1% specified performance

2.5

2.5

V

DC Leakage Current

±1

±1

µA

REFIN Input Impedance

fSAMPLE = 1 MSPS

36

36

kΩ