74HC_HCT112

All information provided in this document is subject to legal disclaimers.

© NXP Semiconductors N.V. 2016. All rights reserved.

Product data sheet

Rev. 3 — 9 August 2016

3 of 20

NXP Semiconductors

74HC112; 74HCT112

Dual JK flip-flop with set and reset; negative-edge trigger

5.

Pinning information

5.1 Pinning

5.2 Pin description

Fig 4.

Pin configuration for SO16

Fig 5.

Pin configuration for (T)SSOP16

Table 2.

Pin description

Symbol

Pin

Description

1CP, 2CP

1, 13

clock input (HIGH-to-LOW; edge-triggered)

1K, 2K

2, 12

data input

1J, 2J

3, 11

data input

1SD, 2SD

4, 10

set input (active LOW)

1Q, 2Q

5, 9

true flip-flop output

1Q, 2Q

6, 7

complement flip-flop output

GND

8

ground (0 V)

1RD, 2RD

15, 14

reset input (active LOW)

VCC

16

supply voltage