74HC_HCT112

All information provided in this document is subject to legal disclaimers.

© NXP Semiconductors N.V. 2016. All rights reserved.

Product data sheet

Rev. 3 — 9 August 2016

10 of 20

NXP Semiconductors

74HC112; 74HCT112

Dual JK flip-flop with set and reset; negative-edge trigger

[1]

All typical values are measured at Tamb =25 C.

[2]

tpd is the same as tPLH and tPHL.

[3]

tt is the same as tTHL and tTLH.

[4]

CPD is used to determine the dynamic power dissipation (PD in W).

PD =CPD  VCC2  fi  N+ (CL  VCC2  fo) where:

fi = input frequency in MHz;

fo = output frequency in MHz;

CL = output load capacitance in pF;

VCC = supply voltage in V;

N = number of inputs switching;

(C

L  VCC

2

 f

o) = sum of outputs.

CPD

power

dissipation

capacitance

CL =50pF;f= 1 MHz;

VI =GND to VCC

[4]

-30

-

-

-

-

-

pF

Table 7.

Dynamic characteristics …continued

Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit, see Figure 8.

Symbol Parameter

Conditions

25

C

40 C to +85 C

40 C to +125 C Unit

Min Typ[1] Max

Min

Max

Min

Max