74HC_HCT112

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© NXP Semiconductors N.V. 2016. All rights reserved.

Product data sheet

Rev. 3 — 9 August 2016

7 of 20

NXP Semiconductors

74HC112; 74HCT112

Dual JK flip-flop with set and reset; negative-edge trigger

10. Dynamic characteristics

Table 7.

Dynamic characteristics

Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit, see Figure 8.

Symbol Parameter

Conditions

25

C

40 C to +85 C

40 C to +125 C Unit

Min Typ[1] Max

Min

Max

Min

Max

74HC112

tpd

propagation

delay

nCP to nQ; see Figure 6

[2]

VCC = 2.0 V

-

55

175

-

220

-

265

ns

VCC = 4.5 V

-

20

35

-

44

-

53

ns

VCC =5V; CL =15pF

-

17

-

-

-

-

-

ns

VCC = 6.0 V

-

16

30

-

37

-

45

ns

nCP to nQ; see Figure 6

VCC = 2.0 V

-

55

175

-

220

-

265

ns

VCC = 4.5 V

-

20

35

-

44

-

53

ns

VCC =5V; CL =15pF

-

17

-

-

-

-

-

ns

VCC = 6.0 V

-

16

30

-

37

-

45

ns

nRD to nQ, nQ;

see Figure 7

VCC = 2.0 V

-

58

180

-

225

-

270

ns

VCC = 4.5 V

-

21

36

-

45

-

54

ns

VCC =5V; CL =15pF

-

18

-

-

-

-

-

ns

VCC = 6.0 V

-

17

31

-

38

-

46

ns

nSD to nQ, nQ;

see Figure 7

VCC = 2.0 V

-

50

155

-

295

-

235

ns

VCC = 4.5 V

-

18

31

-

39

-

47

ns

VCC =5V; CL =15pF

-

15

-

-

-

-

-

ns

VCC = 6.0 V

-

14

26

-

33

-

40

ns

tt

transition

time

nQ, nQ; see Figure 6

[3]

VCC = 2.0 V

-

19

75

-

95

-

110

ns

VCC = 4.5 V

-

7

15

-

19

-

22

ns

VCC = 6.0 V

-

6

13

-

16

-

19

ns

tW

pulse width

nCP HIGH or LOW;

see Figure 6

VCC = 2.0 V

80

22

-

100

-

120

-

ns

VCC = 4.5 V

16

8

-

20

-

24

-

ns

VCC = 6.0 V

14

6

-

17

-

20

-

ns

nSD, nRD LOW;

see Figure 7

VCC = 2.0 V

80

22

-

100

-

120

-

ns

VCC = 4.5 V

16

8

-

20

-

24

-

ns

VCC = 6.0 V

14

6

-

17

-

20

-

ns