1.

General description

The 74HC259; 74HCT259 is an 8-bit addressable latch. The device features four modes

of operation. In the addressable latch mode, data on the D input is written into the latch

addressed by the inputs AO to A3. The addressed latch will follow the data input,

non-addressed latches will retain their previous states. In memory mode, all latches retain

their previous states and are unaffected by the data or address inputs. In the 3-to-8

decoding or demultiplexing mode, the addressed output follows the D input and all other

outputs are LOW. In the reset mode, all outputs are forced LOW and unaffected by the

data or address inputs. Inputs include clamp diodes. This enables the use of current

limiting resistors to interface inputs to voltages in excess of VCC.

2.

Features and benefits

 Combined demultiplexer and 8-bit latch

 Serial-to-parallel capability

 Output from each storage bit available

 Random (addressable) data entry

 Easily expandable

 Common reset input

 Useful as a 3-to-8 active HIGH decoder

 Complies with JEDEC standard no. 7A

 Input levels:

 For 74HC259: CMOS level

 For 74HCT259: TTL level

 ESD protection:

 HBM JESD22-A114F exceeds 2000 V

 MM JESD22-A115-A exceeds 200 V

 CDM JESD22E exceeds 1000 V

 Multiple package options

 Specified from

40 C to +85 C and from 40 C to +125 C

74HC259; 74HCT259

8-bit addressable latch

Rev. 6 — 2 February 2016

Product data sheet