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74HC259D Datasheet(PDF) 13 Page - Nexperia B.V. All rights reserved |
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74HC259D Datasheet(HTML) 13 Page - Nexperia B.V. All rights reserved |
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13 / 21 page ![]() 74HC_HCT259 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. Product data sheet Rev. 6 — 2 February 2016 13 of 21 NXP Semiconductors 74HC259; 74HCT259 8-bit addressable latch Test data is given in Table 10. Definitions test circuit: RT = Termination resistance should be equal to output impedance Zo of the pulse generator. CL = Load capacitance including jig and probe capacitance. RL = Load resistance. S1 = Test selection switch Fig 12. Test circuit for measuring switching times Table 10. Test data Type Input Load S1 position VI tr, tf CL RL tPHL, tPLH 74HC259 VCC 6ns 15pF, 50 pF 1k open 74HCT259 3V 6ns 15pF, 50 pF 1k open |
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