74HC_HCT595

All information provided in this document is subject to legal disclaimers.

© NXP Semiconductors N.V. 2016. All rights reserved.

Product data sheet

Rev. 8 — 25 February 2016

5 of 23

NXP Semiconductors

74HC595; 74HCT595

8-bit serial-in, serial or parallel-out shift register with output latches; 3-state

7.

Functional description

[1]

H = HIGH voltage state;

L = LOW voltage state;

 = LOW-to-HIGH transition;

X = don’t care;

NC = no change;

Z = high-impedance OFF-state.

Table 3.

Function table[1]

Control

Input

Output

Function

SHCP STCP OE

MR

DS

Q7S

Qn

X

X

L

L

X

L

NC

a LOW-level on MR only affects the shift registers

X



L

L

X

L

L

empty shift register loaded into storage register

X

X

H

L

X

L

Z

shift register clear; parallel outputs in high-impedance OFF-state



X

L

H

H

Q6S

NC

logic HIGH-level shifted into shift register stage 0. Contents of all

shift register stages shifted through, e.g. previous state of stage 6

(internal Q6S) appears on the serial output (Q7S).

X



L

H

X

NC

QnS

contents of shift register stages (internal QnS) are transferred to

the storage register and parallel output stages



L

H

X

Q6S

QnS

contents of shift register shifted through; previous contents of the

shift register is transferred to the storage register and the parallel

output stages

Fig 7.

Timing diagram