Circuit Note

CN-0582

analog.com

Rev. A | 5 of 10

IEPE Input Offsetting

IEPE signals naturally have a high dc bias and peak-to-peak val-

ues, making it difficult to interface with common smaller range

converters. To overcome this challenge, a level shifting circuit is

used.

Figure 5 shows the level shifter implementation based on the

ADA4522. The attenuation and voltage shift are designed to utilize

the full ±4.096 V ADC input range by centering the input as close as

possible to zero.

Figure 5. Level Shifting Circuit

The required voltage shift is calculated using Equation 4:

VSHIFT=VIEPE_SHIFTED +G VIEPE_INPUT 

1+G

(4)

where:

VSHIFT is the level shift voltage.

VIEPE_INPUT is the input bias voltage.

VIEPE_SHIFTED is 2.52 (must be equal to VOCM).

G is 0.3 (computed as

RFBRIN).

The level shift voltage (VSHIFT) is provided by the AD5686R digi-

tal-to-analog converter (DAC). The value of VSHIFT can be program-

med using Equation 5:

D= VSHIFT ×2n

VREF ×Gain

(5)

where:

VSHIFT is the level shift voltage.

VREF is the voltage reference of AD5686R.

Gain is the gain setting of AD5686R.

D is the digital code.

N is the number of bits of AD5686R (16-bit).

PROGRAMMABLE GAIN AMPLIFIER (PGA)

Aside from the input signal coupling and level shifting options, the

CN0582 also provides additional gain for smaller input signals. The

gain can be set for each individual analog input channel.

Figure 6 shows the PGA implementation using the LTC6910. The

common-mode voltage from the other signal conditioning stages

is connected to the AGND pin, which serves as the reference for

amplification.

Figure 6. Programmable Gain Amplifier

Depending on the gain option selected, the valid input range for

the CN0582 also changes. Table 2 describes the acceptable input

voltage range for each gain setting; voltages outside the valid input

range result in signal distortion and clipping.

Table 2. EVAL-CN0582-USBZ PGA Settings vs. Input Voltage

PGA Settings

Maximum AC Input

1

10 Vp-p

2

5 Vp-p

5

2 Vp-p

10

1 Vp-p

20

500 mVp-p

50

200 mVp-p

100

100 mVp-p

Note: The system can measure signal amplitudes of 100 μVp-p,

but the signal-to-noise ratio (SNR) is compromised. Thus, the

recommended minimum input amplitude is 500 μVp-p.

FULLY DIFFERENTIAL AMPLIFIER (FDA)

Since the output signal of the PGA is a pseudo-differential signal

with a common-mode of 2.5 V, it needs to be amplified and convert-

ed to a fully differential signal to maximize the use of the ADC’s full

scale input range of 8.192 Vp-p.

Figure 7 shows the ADA4945 fully differential ADC driver used to

convert the pseudo-differential signal from the PGA to a fully-differ-

ential signal for the ADC.

Figure 7. Single-to-Differential Driver Circuit