Circuit Note

CN-0582

analog.com

Rev. A | 6 of 10

The PGA output with respect to VOCM is amplified and converted

to a fully differential signal by the ADA4945 with a gain shown in

Equation 6:

G=RfRi=2000750=2.667

(6)

In case of over or undervoltage due to the input and gain combina-

tions, the ADA4945 clamps the output to +VS or -VS to protect the

succeeding sensitive ADC input stage.

OVERALL SIGNAL CHAIN GAIN

The total gain on the analog input path comes from the level shifter,

FDA, and PGA, which can be computed using Equation 7:

G=G1×G2×GPGA

(7)

G=0.3×2.667×GPGA

G=0.8GPGA

where:

G is the overall system gain of the CN0582.

G1 is the gain of the level shift attenuation (0.3).

G2 is the gain of the FDA (2.667).

GPGA is the programmable gain of the PGA (1, 2, 5, 10, 20, 50,

100).

The maximum allowable ac or dc voltage on the analog input path

is directly related to the gain settings of each channel. Equation 8

shows how to calculate the dc input voltage, assuming a PGA gain

setting of 1.

VINDC_MAX =VSHIFT_MAX ×1 + G1−VOCM

G1

(8)

The maximum dc bias input voltage is:

VINDC_MAX =13.26V

where:

VINDC_MAX is the maximum dc voltage into the CN0582.

VSHIFT_MAX is the AD5686R maximum output voltage (5 V).

G1 is the gain of the level shift attenuation (0.3).

VOCM is the AD7768-4 common-mode voltage (2.52 V).

The ac input voltage can be computed using Equation 9, assuming

that the PGA gain setting is 1.

VINAC_MAX = VREF_ADCG2G1 ×2

(9)

The maximum peak-to-peak input voltage swing is:

VINAC_MAX =10.23Vp‐p

where:

VINAC_MAX is the maximum ac input voltage into the CN0582.

VREF_ADC is the AD7768-4 internal voltage reference (4.096 V).

G2 is the gain of FDA (2.667)

G1 is the gain of the level shift attenuation (0.3)

The theoretical maximum ac input swing is 10.23 Vp-p, but the

CN0582 is only tested up to 10 Vp-p to meet the headroom

requirements of the amplifiers. The same logic applies to maximum

dc bias, which was only tested to 13 VDC. Centering the ADC

output around zero by adjusting VSHIFT implies the IEPE_SHIFTED

signal is equal to VOCM.

DATA CAPTURE AND DIGITAL CONTROLLER

Analog-to-digital conversion is performed by an AD7768-4, a 4-

channel 24-bit simultaneous sampling Σ-Δ ADC. It contains several

power scaling, filter, and sample rate options to optimize for differ-

ent constraints like noise, bandwidth, and power consumption.

The AD7768-4 acts as a source-synchronous transmitter, with each

channel’s data serialized on one of four data lines. The data is

received by the digital controller and streamed to the host computer

over USB.

The digital controller is also responsible for configuring the analog

input channels, enabling the current sources, setting the ADC

modes, and setting up the waveform generator.

POWER SUPPLY ARCHITECTURE

The CN0582 is powered from a single USB 3.0 port providing 5 V

at 900 mA, and several dc-to-dc converters produce the required

voltage rails. The system power tree consists of boost converters

followed by linear dropout regulators for the analog circuits to obtain

the lowest possible noise, and buck converters for digital circuits

for maximum efficiency. Figure 8 presents the complete power

architecture of CN0582.

Figure 8. CN0582 System Power Tree