M2006-02A Datasheet Rev 1.0

7 of 8

Revised 28Jul2004

Integr ated Circuit Systems , Inc. ● Ne tw o r ki ng & C o mmun ica t io ns ● ww w. icst.com ● tel (508 ) 85 2-54 00

M2006-02A

Prod uct Data Sh eet

Integrated

Circuit

Systems, Inc.

Output Rise and Fall Time

Figure 5: Output Rise and Fall Time

Output Duty Cycle

Figure 6: Output Duty Cycle

AC Characteristics

Unless stated otherwise, V

LVPECL outputs terminated with 50

Ω to V

Symbol Parameter

Min

Typ

Max

Unit Test Conditions

Input

Frequency

Range

F

IN

Input Frequency

DIF_REF0, nDIF_REF0,

DIF_REF1, nDIF_REF1

10

700

MHz

Output

Frequency

F

FOUT

Output Frequency

Range

FOUT0, nFOUT0,

FOUT1, nFOUT1

100

700

MHz

APR

VCSO Pull-Range

Commercial

ppm

Industrial

ppm

PLL Loop

Note 1: Parameters needed for PLL Simulator software; see Table 8, Example External Loop Filter Component Values, on pg. 5.

K

VCO

VCO Gain

800

kHz/V

R

IN

Internal Loop Resistor

50

k

Ω

BW

VCSO

VCSO Bandwidth

700

kHz

Phase Noise

and Jitter

Φn

Single Side Band

Phase Noise

1

kHz Offset

dBc/Hz

Fin=19.44 MHz

Mfin=32, Mfec=1, Rfec=1

10

kHz Offset

dBc/Hz

100

kHz Offset

dBc/Hz

J(t)

Jitter (rms)

12kHz to 20MHz

0.25

0.5

ps rms

50kHz to 80MHz

0.25

0.5

ps rms

t

PW

FOUT0, nFOUT0,

FOUT1, nFOUT1

Note 2: See Parameter Measurement Information on pg. 7.

P0, P1 = 1

40

50

60

%

P0, P1 = 4

45

50

55

%

t

R

FOUT0, nFOUT0,

FOUT1, nFOUT1

200

450

500

ps

20

t

F

200

450

500

ps

20

Table 12: AC Characteristics

20%

80%

20%

80%

Clock Output

V

P

nFOUT

FOUT

t

PW

t

PERIOD

(Output Pulse Width)

odc =