M2006-02A Datasheet Rev 1.0

Revised 28Jul2004

Integr ated Circuit Systems , Inc. ● Ne tw o r ki ng & C o mmun ica t io ns ● ww w. icst.com ● tel (508 ) 85 2-5 400

M2006-02A

Integrated

Circuit

Systems, Inc.

Product Data Sheet

The M2006-02A is a VCSO (Voltage Controlled SAW

Oscillator) based clock generator

PLL designed for clock frequency

translation and jitter attenuation.

The device supports both forward

and inverse FEC (Forward Error

Correction) clock multiplication

ratios. Multiplication ratios are

pin-selected from pre-programming look-up tables.

◆ Reduced intrinsic output jitter and improved power

supply noise rejection compared to M2006-02

◆ Low phase jitter of 0.25 ps rms typical

(12kHz to 20MHz or 50kHz to 80MHz)

◆ Pin-selectable PLL divider ratios support forward and

inverse FEC ratio translation, including:

• 255/238 (OTU1) Mapping and 238/255 De-mapping

• 255/237 (OTU2) Mapping and 237/255 De-mapping

• 255/236 (OTU3) Mapping and 236/255 De-mapping

◆ Input reference and VCSO frequencies up to 700MHz,

supports loop timing modes

(Specify VCSO frequency at time of order)

◆ Supports active switching between inverse-FEC and

non-FEC clock ratios (same VCSO center frequency)

◆ Ideal for complex ratio FEC ratio translation and

for use with an unstable reference (i.e., similar to the

Hitless Switching and Phase Build-out functions)

◆ Single 3.3V power supply

◆ Small 9 x 9 mm SMT (surface mount) package

Figure 1: Pin Assignment

Example I/O Clock Combinations

Figure 2: Simplified Block Diagram

Using M2006-02A-622.0800

PLL Ratio

Input Clock (MHz)

Output Clock (MHz)

1/1

622.08, 155.52,

77.76, or 19.44

622.08

or

155.52

237/255

(inverse FEC)

669.3266, 167.3316,

83.6658, or 20.9165

Table 1: Example I/O Clock Combinations Using M2006-02A-622.0800

Using M2006-02A-669.3266

PLL Ratio

Input Clock (MHz)

Output Clock (MHz)

237/255

(FEC rate)

622.08, 155.52,

77.76, or 19.44

669.3266

or

167.3316

1/1

669.3266, 167.3316,

83.6658, or 20.9165

Table 2: Example I/O Clock Combinations Using M2006-02A-669.3266

M 200 6- 02

( T op View )

18

17

16

15

14

13

12

11

10

28

29

30

31

32

33

34

35

36

P0_SEL

P1_SEL

nFOUT0

FOUT0

GND

nFOUT1

FOUT1

VCC

GND

FIN_SEL0

FEC_SEL0

FEC_SEL1

FEC_SEL2

FEC_SEL3

VCC

DNC

DNC

DNC

A

Rfec Div

Mfec Div

Mfec / Rfec

Divider LUT

Mfin Divider

LUT

FIN_SEL1:0

REF_SEL

DIF_REF0

nDIF_REF0

DIF_REF1

nDIF_REF1

P0_SEL

P1_SEL

VCSO

0

1

M2006-02

FOUT0

nFOUT0

FOUT1

nFOUT1

FEC_SEL3:0

4

2

P0 Div

(1 or 4)

Mfin Div

(1, 4, 8, or 32)

P1 Div

(1 or 4)

Loop

Filter

A

M2006-02A VCSO Based FEC Clock PLL