ADS5482 datasheet(7/35 Pages) TI

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TIMING INFORMATION

N+1

Dx_y_P

N+2

N+6

CLKL

DRY

DATA

CLKH

Dx_y_M

CLKP

CLKM

N+3

N+4

N+5

DRY_M

DRY_P

Sample

T0158-02

Latency = 4.5 Clock Cycles

CLK

Input

CLK

Output

Data

N+1

N–1

N–2

N–3

N–4

N–5

E=EvenBits=B0,B2,B4,B6,B8,B10,B12,B14

O =OddBits=B1,B3,B5,B7,B9,B11,B13,B15

TIMING CHARACTERISTICS

(1)

ADS5481

ADS5482, ADS5483

www.ti.com ...................................................................................................................................................................................................... SLAS565 – JUNE 2008

Figure 1. Timing Diagram

Typical values at TA = +25°C: minimum and maximum values over full temperature range TMIN = –40°C to TMAX = +85°C,

sampling rate = Max Rated, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V, and 3-VPP differential

clock, unless otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Aperture delay

200

Aperture jitter, rms

Internal jitter of the ADC

Latency

4.5

cycles

tCLK

Clock period

1e9/CLK

100

tCLKH

Clock pulse duration, high

CLK = max rated clock for that part number

0.5e9/CLK

tCLKL

Clock pulse duration, low

0.5e9/CLK

tDRY

CLK to DRY delay(2)

800

1250

1700

Zero crossing, 5-pF parasitic to GND

tDATA

CLK to DATA delay(2)

700

1250

1800

tSKEW

DATA to DRY skew

tDATA – tDRY, 5-pF parasitic to GND

–600

600

tRISE

DRY/DATA rise time

500

5-pF parasitic to GND

tFALL

DRY/DATA fall time

500

(1)

Timing parameters are assured by design or characterization, but not production tested.

(2)

DRY and DATA are updated on the rising edge of CLK input. The latency must be added to tDATA to determine the overall propagation

delay.

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