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ADS7229IPW Datasheet(PDF) 35 Page - Texas Instruments |
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ADS7229IPW Datasheet(HTML) 35 Page - Texas Instruments |
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35 / 46 page ![]() EOC#1 (activelow) CONVST #2=1 FS/ #1 CS INT (activelow) Common S K CL C s a c d a ed M n a ual Tr a ig h ge W r/Read ile S mpling (UseinternalCCLK,EOC,and programmedasactivelow) heldlowduringtheNtimes16bitstransfercycle INT CS SDO#2 SDI t CONV =18CCLKs 1……………………16 1101b READResult 1……………………16 Nth 1……………………16 1101b READResult FS/ #2 CS FS/ #3 CS SDO#1 Nthfrom #1 SDO#3 N 1th# - 2 Nthfrom #3 Nthfrom #1 Nthfrom #1 N 1th# - 2 t 4 t 4 CONVST #1 CONVST #3 READResult 1101b t SAMPLE1 =3CCL n KsMi ADS7229 ADS7230 www.ti.com........................................................................................................................................................................................................ SBAS437 – MAY 2008 Figure 64 shows a slightly different scenario where CONVST is not shared by the second converter. Converters #1 and #3 have the same CONVST signal. In this case, converter #2 simply passes the previous conversion data downstream. Figure 64. Simplified Cascade Timing (Separate CONVST) The number of SCLKs required for a serial read cycle depends on the combination of different read modes, TAG bit, chain mode, and the way a channel is selected (that is, auto channel select). These possible configurations are listed in Table 6. Table 6. Required SCLKs For Different Read Out Mode Combinations CHAIN MODE AUTO CHANNEL NUMBER OF SCLK PER SPI ENABLED CFR.D5 SELECT CFR.D11 TAG ENABLED CFR.D1 READ TRAILING BITS 0 0 0 12 None 0 0 1 ≥ 17 MSB is TAG bit plus zero(s) 0 1 0 12 None 0 1 1 ≥ 17 TAG bit plus seven zeros 1 0 0 16 None 1 0 1 24 TAG bit plus seven zeros 1 1 0 16 None 1 1 1 24 TAG bit plus seven zeros Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 35 Product Folder Link(s): ADS7229 ADS7230 |
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