TAS5705PAP datasheet(43/71 Pages) TI

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Interchannel Delay (ICD) Settings

TAS5705

www.ti.com ...................................................................................................................................................................................................... SLOS549 – JUNE 2008

By default, bits 2:0 have the value 000; that means the bank switch is disabled. In that state, any update to

locations 0x29–0x3F go into the DAP. A write to register 0x50 with bits 2:0 being 001, 010, or 011 brings the

system into the coefficient-bank-update state update bank1, update bank2, or update bank3, respectively. Any

subsequent write to locations 0x29–0x3F updates the coefficient banks stored outside the DAP. After updating all

the three banks, the system controller should issue a write to register 0x50 with bits 2:0 being 100; this changes

the system state to automatic bank update. In automatic bank update, the TAS5705 automatically swaps banks

based on the sample rate.

In the headphone mode, speaker equalization and DRC are disabled, and they are restored on returning to the

speaker mode.

Command sequences for initialization can be summarized as follows:

Enable factory trim for internal oscillator: Write to register 0x1B with a value 0x00.

Update coefficients: Coefficients can be loaded into DAP RAM using the manual bank mode.

Use automatic bank mode.

Enable bank-1 mode: Write to register 0x50 with 0x01. Load the 32-kHz coefficients. TI ALE

can generate coefficients.

Enable bank-2 mode: Write to register 0x50 with 0x02. Load the 48-kHz coefficients.

Enable bank-3 mode: Write to register 0x50 with 0x03. Load the other coefficients.

Enable automatic bank switching by writing to register 0x50 with 0x04.

Bring the system out of all-channel shutdown: Write 0 to bit 6 of register 0x05.

Issue master volume: Write to register 0x07 with the volume value (0 db = 0x30).

Table 6. Recommended ICD Settings

Mode

Description

ICD1

ICD2

ICD3

ICD4

ICD5

ICD6

2 BTL channels, internal

A(L+) = –18

C(R+) = 24 =

B(L–) = –24 =

D(R–) = 18 =

SM(S–) = –3 =

SP(S+) = 3 =

power stage only, BD

(0xB8)

(0x60)

(0xA0)

(0x48)

(0xF4)

(0x0C)

mode

2 internal BTL channels,

A(L+) = 21 =

C(R+) = 21

B(L–) = –21 =

D(R–) = 21 =

SM(S–) = 0 =

SP(S+) = 0 =

1 external BTL channel

(0xAC)

(0x54)

(0xAC)

(0x54)

(0x00)

using PBTL TAS5601,

AD mode

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